mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-23 20:15:35 +00:00
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
instructions on having SSE2. llvm-svn: 55317
This commit is contained in:
parent
df2af1f4c5
commit
f86b246fdb
@ -157,16 +157,20 @@ class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
|
||||
// SSE2 Instruction Templates:
|
||||
//
|
||||
// SDI - SSE2 instructions with XD prefix.
|
||||
// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
|
||||
// PDI - SSE2 instructions with TB and OpSize prefixes.
|
||||
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
|
||||
// SDI - SSE2 instructions with XD prefix.
|
||||
// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
|
||||
// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
|
||||
// PDI - SSE2 instructions with TB and OpSize prefixes.
|
||||
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
|
||||
|
||||
class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
|
||||
class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
|
||||
class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern>
|
||||
: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
|
||||
class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
|
||||
: I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
|
||||
class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
|
@ -173,15 +173,15 @@ def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
|
||||
"movq\t{$src, $dst|$dst, $src}",
|
||||
[(store (v1i64 VR64:$src), addr:$dst)]>;
|
||||
|
||||
def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
|
||||
def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
|
||||
"movdq2q\t{$src, $dst|$dst, $src}",
|
||||
[(set VR64:$dst,
|
||||
(v1i64 (bitconvert
|
||||
(i64 (vector_extract (v2i64 VR128:$src),
|
||||
(iPTR 0))))))]>;
|
||||
|
||||
def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
|
||||
"movq2dq\t{$src, $dst|$dst, $src}",
|
||||
def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
|
||||
"movq2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(v2i64 (vector_shuffle immAllZerosV,
|
||||
(v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
|
||||
|
Loading…
Reference in New Issue
Block a user