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https://github.com/RPCS3/llvm-mirror.git
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Use a couple of multiclass patterns to factor some integer ops.
llvm-svn: 30039
This commit is contained in:
Chris Lattner
parent
04b7417f40
commit
fa87f12b85
@ -109,3 +109,5 @@ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag ops,
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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@ -168,6 +168,32 @@ def FCC_LE : FCC_VAL<27>; // Less or Equal
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def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
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def FCC_O : FCC_VAL<29>; // Ordered
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
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multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
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def rr : F3_1<2, Op3Val,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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!strconcat(OpcStr, " $b, $c, $dst"),
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[(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
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def ri : F3_2<2, Op3Val,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $b, $c, $dst"),
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[(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
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}
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/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
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/// pattern.
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multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
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def rr : F3_1<2, Op3Val,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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!strconcat(OpcStr, " $b, $c, $dst"), []>;
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def ri : F3_2<2, Op3Val,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $b, $c, $dst"), []>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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@ -364,14 +390,8 @@ let rd = 0, imm22 = 0 in
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def NOP : F2_1<0b100, (ops), "nop", []>;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"and $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
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def ANDri : F3_2<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"and $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
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defm AND : F3_12<"and", 0b000001, and>;
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def ANDNrr : F3_1<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andn $b, $c, $dst",
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@ -379,14 +399,9 @@ def ANDNrr : F3_1<2, 0b000101,
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def ANDNri : F3_2<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andn $b, $c, $dst", []>;
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def ORrr : F3_1<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"or $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
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def ORri : F3_2<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"or $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
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defm OR : F3_12<"or", 0b000010, or>;
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def ORNrr : F3_1<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orn $b, $c, $dst",
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@ -394,14 +409,8 @@ def ORNrr : F3_1<2, 0b000110,
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def ORNri : F3_2<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orn $b, $c, $dst", []>;
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def XORrr : F3_1<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xor $b, $c, $dst",
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[(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
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def XORri : F3_2<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xor $b, $c, $dst",
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[(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
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defm XOR : F3_12<"xor", 0b000011, xor>;
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def XNORrr : F3_1<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnor $b, $c, $dst",
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@ -411,40 +420,12 @@ def XNORri : F3_2<2, 0b000111,
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"xnor $b, $c, $dst", []>;
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sll $b, $c, $dst",
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[(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
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def SLLri : F3_2<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sll $b, $c, $dst",
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[(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
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def SRLrr : F3_1<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"srl $b, $c, $dst",
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[(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
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def SRLri : F3_2<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"srl $b, $c, $dst",
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[(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
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def SRArr : F3_1<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sra $b, $c, $dst",
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[(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
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def SRAri : F3_2<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sra $b, $c, $dst",
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[(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
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defm SLL : F3_12<"sll", 0b100101, shl>;
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defm SRL : F3_12<"srl", 0b100110, srl>;
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defm SRA : F3_12<"sra", 0b100111, sra>;
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"add $b, $c, $dst",
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[(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
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def ADDri : F3_2<2, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"add $b, $c, $dst",
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[(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
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defm ADD : F3_12<"add", 0b000000, add>;
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// "LEA" forms of add (patterns to make tblgen happy)
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def LEA_ADDri : F3_2<2, 0b000000,
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@ -452,97 +433,30 @@ def LEA_ADDri : F3_2<2, 0b000000,
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"add ${addr:arith}, $dst",
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[(set IntRegs:$dst, ADDRri:$addr)]>;
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def ADDCCrr : F3_1<2, 0b010000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addcc $b, $c, $dst",
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[(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))]>;
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def ADDCCri : F3_2<2, 0b010000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addcc $b, $c, $dst",
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[(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))]>;
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def ADDXrr : F3_1<2, 0b001000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addx $b, $c, $dst",
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[(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))]>;
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def ADDXri : F3_2<2, 0b001000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addx $b, $c, $dst",
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[(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))]>;
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defm ADDCC : F3_12<"addcc", 0b010000, addc>;
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defm ADDX : F3_12<"addx", 0b001000, adde>;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sub $b, $c, $dst",
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[(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
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def SUBri : F3_2<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sub $b, $c, $dst",
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[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
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def SUBXrr : F3_1<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subx $b, $c, $dst",
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[(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))]>;
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def SUBXri : F3_2<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subx $b, $c, $dst",
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[(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))]>;
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst",
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[(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>;
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def SUBCCri : F3_2<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subcc $b, $c, $dst",
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[(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>;
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defm SUB : F3_12 <"sub" , 0b000100, sub>;
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defm SUBX : F3_12 <"subx" , 0b001100, sube>;
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defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
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def SUBXCCrr: F3_1<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subxcc $b, $c, $dst", []>;
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"umul $b, $c, $dst", []>;
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def UMULri : F3_2<2, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"umul $b, $c, $dst", []>;
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def SMULrr : F3_1<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"smul $b, $c, $dst",
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[(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
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def SMULri : F3_2<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"smul $b, $c, $dst",
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[(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
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defm UMUL : F3_12np<"umul", 0b001010>;
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defm SMUL : F3_12 <"smul", 0b001011, mul>;
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// Section B.19 - Divide Instructions, p. 115
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def UDIVrr : F3_1<2, 0b001110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"udiv $b, $c, $dst", []>;
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def UDIVri : F3_2<2, 0b001110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"udiv $b, $c, $dst", []>;
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def SDIVrr : F3_1<2, 0b001111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sdiv $b, $c, $dst", []>;
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def SDIVri : F3_2<2, 0b001111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sdiv $b, $c, $dst", []>;
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defm UDIV : F3_12np<"udiv", 0b001110>;
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defm SDIV : F3_12np<"sdiv", 0b001111>;
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// Section B.20 - SAVE and RESTORE, p. 117
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def SAVErr : F3_1<2, 0b111100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"save $b, $c, $dst", []>;
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def SAVEri : F3_2<2, 0b111100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"save $b, $c, $dst", []>;
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def RESTORErr : F3_1<2, 0b111101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"restore $b, $c, $dst", []>;
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def RESTOREri : F3_2<2, 0b111101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"restore $b, $c, $dst", []>;
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defm SAVE : F3_12np<"save" , 0b111100>;
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defm RESTORE : F3_12np<"restore", 0b111101>;
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// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
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