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[AArch64] Reverting FP16 vcvth_n_s64_f16 to fix
llvm-svn: 335737
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@ -4979,8 +4979,6 @@ def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 (sext_inreg FPR32:$Rn, i16)), v
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(SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
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def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i32 FPR32:$Rn), vecshiftR16:$imm)),
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(SCVTFh (EXTRACT_SUBREG FPR32:$Rn, hsub), vecshiftR16:$imm)>;
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def : Pat<(f16 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR16:$imm)),
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(SCVTFh (EXTRACT_SUBREG FPR64:$Rn, hsub), vecshiftR16:$imm)>;
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def : Pat<(f16 (int_aarch64_neon_vcvtfxu2fp
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(and FPR32:$Rn, (i32 65535)),
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vecshiftR16:$imm)),
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@ -176,26 +176,6 @@ entry:
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ret half %vcvth_n_f16_s32
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}
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define dso_local half @test_vcvth_n_f16_s64_1(i64 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s64_1:
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; CHECK: fmov d0, x0
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; CHECK-NEXT: scvtf h0, h0, #1
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 1)
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ret half %vcvth_n_f16_s64
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}
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define dso_local half @test_vcvth_n_f16_s64_16(i64 %a) {
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; CHECK-LABEL: test_vcvth_n_f16_s64_16:
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; CHECK: fmov d0, x0
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; CHECK-NEXT: scvtf h0, h0, #16
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; CHECK-NEXT: ret
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entry:
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%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)
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ret half %vcvth_n_f16_s64
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}
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define dso_local i16 @test_vcvth_n_s16_f16_1(half %a) {
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; CHECK-LABEL: test_vcvth_n_s16_f16_1:
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; CHECK: fcvtzs h0, h0, #1
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