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Fix combine of uno && ord -> false so that the ordering of the fcmps doesn't
matter. rdar://11579835 llvm-svn: 158084
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@ -986,6 +986,9 @@ Value *InstCombiner::FoldAndOfFCmps(FCmpInst *LHS, FCmpInst *RHS) {
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bool Op1Ordered;
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unsigned Op0Pred = getFCmpCode(Op0CC, Op0Ordered);
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unsigned Op1Pred = getFCmpCode(Op1CC, Op1Ordered);
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// uno && ord -> false
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if (Op0Pred == 0 && Op1Pred == 0 && Op0Ordered != Op1Ordered)
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return ConstantInt::get(CmpInst::makeCmpResultType(LHS->getType()), 0);
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if (Op1Pred == 0) {
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std::swap(LHS, RHS);
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std::swap(Op0Pred, Op1Pred);
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@ -998,7 +1001,6 @@ Value *InstCombiner::FoldAndOfFCmps(FCmpInst *LHS, FCmpInst *RHS) {
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return RHS;
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// uno && oeq -> uno && (ord && eq) -> false
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// uno && ord -> false
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if (!Op0Ordered)
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return ConstantInt::get(CmpInst::makeCmpResultType(LHS->getType()), 0);
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// ord && ueq -> ord && (uno || eq) -> oeq
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@ -56,3 +56,13 @@ define zeroext i8 @t5(float %x, float %y) nounwind {
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; CHECK: t5
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; CHECK: ret i8 0
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}
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define zeroext i8 @t6(float %x, float %y) nounwind {
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%a = fcmp uno float %x, %y
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%b = fcmp ord float %x, %y
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%c = and i1 %a, %b
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%retval = zext i1 %c to i8
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ret i8 %retval
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; CHECK: t6
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; CHECK: ret i8 0
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}
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