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[X86] Remove the vector alignment requirement from the patterns added in r337320.

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The resulting instruction will only load 64 bits so alignment isn't required.

llvm-svn: 337334
This commit is contained in:
Craig Topper 2018-07-17 23:26:20 +00:00
parent 52168cfcad
commit fb87d54a09
2 changed files with 6 additions and 4 deletions
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6
lib/Target/X86/X86InstrSSE.td
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@ -725,7 +725,8 @@ let Predicates = [UseSSE1] in {
// This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll
// end up with a movsd or bleand instead of shufp.
def : Pat<(X86Shufp (memopv4f32 addr:$src2), VR128:$src1, (i8 -28)),
// No need for aligned load, we're only loading 64-bits.
def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)),
(MOVLPSrm VR128:$src1, addr:$src2)>;
}
@ -801,7 +802,8 @@ let Predicates = [UseSSE1] in {
// This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll
// end up with a movsd or bleand instead of shufp.
def : Pat<(X86Movlhps VR128:$src1, (memopv4f32 addr:$src2)),
// No need for aligned load, we're only loading 64-bits.
def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)),
(MOVHPSrm VR128:$src1, addr:$src2)>;
}

4
test/CodeGen/X86/vector-shuffle-sse1.ll
View File

@ -280,7 +280,7 @@ define <4 x float> @shuffle_mem_v4f32_0145(<4 x float> %a, <4 x float>* %pb) {
; SSE1: # %bb.0:
; SSE1-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; SSE1-NEXT: retq
%b = load <4 x float>, <4 x float>* %pb, align 16
%b = load <4 x float>, <4 x float>* %pb, align 1
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x float> %shuffle
}
@ -300,7 +300,7 @@ define <4 x float> @shuffle_mem_v4f32_4523(<4 x float> %a, <4 x float>* %pb) {
; SSE1: # %bb.0:
; SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
; SSE1-NEXT: retq
%b = load <4 x float>, <4 x float>* %pb, align 16
%b = load <4 x float>, <4 x float>* %pb, align 1
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x float> %shuffle
}