RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:39:57 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[AMDGPU][MC][DOC] A fix for build failure in r349370

Browse Source 
llvm-svn: 349375
This commit is contained in:
Dmitry Preobrazhensky 2018-12-17 18:53:10 +00:00
parent 46b5003273
commit fbb8f7bee4
22 changed files with 61 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/AMDGPU/gfx7_attr.rst
View File

@ -23,7 +23,7 @@ Interpolation attribute and channel:
Examples:
.. code-block:: nasm
.. parsed-literal::
v_interp_p1_f32 v1, v0, attr0.x
v_interp_p1_f32 v1, v0, attr32.w

2
docs/AMDGPU/gfx7_hwreg.rst
View File

@ -51,7 +51,7 @@ Defined register *names* include:
Examples:
.. code-block:: nasm
.. parsed-literal::
s_getreg_b32 s2, 0x6
s_getreg_b32 s2, hwreg(15)

2
docs/AMDGPU/gfx7_label.rst
View File

@ -20,7 +20,7 @@ This operand may be specified as:
Examples:
.. code-block:: nasm
.. parsed-literal::
offset = 30
s_branch loop_end

2
docs/AMDGPU/gfx7_msg.rst
View File

@ -60,7 +60,7 @@ Each message type supports specific operations:
Examples:
.. code-block:: nasm
.. parsed-literal::
s_sendmsg 0x12
s_sendmsg sendmsg(MSG_INTERRUPT)

2
docs/AMDGPU/gfx7_src_exp.rst
View File

@ -19,7 +19,7 @@ Data to copy to export buffers. This is an optional operand. Must be specified a
An example:
.. code-block:: nasm
.. parsed-literal::
exp mrtz v3, v3, off, off compr

2
docs/AMDGPU/gfx7_waitcnt.rst
View File

@ -44,7 +44,7 @@ These helpers may be specified in any order. Ampersands and commas may be used a
Examples:
.. code-block:: nasm
.. parsed-literal::
s_waitcnt 0
s_waitcnt vmcnt(1)

2
docs/AMDGPU/gfx8_attr.rst
View File

@ -23,7 +23,7 @@ Interpolation attribute and channel:
Examples:
.. code-block:: nasm
.. parsed-literal::
v_interp_p1_f32 v1, v0, attr0.x
v_interp_p1_f32 v1, v0, attr32.w

2
docs/AMDGPU/gfx8_hwreg.rst
View File

@ -51,7 +51,7 @@ Defined register *names* include:
Examples:
.. code-block:: nasm
.. parsed-literal::
s_getreg_b32 s2, 0x6
s_getreg_b32 s2, hwreg(15)

2
docs/AMDGPU/gfx8_label.rst
View File

@ -20,7 +20,7 @@ This operand may be specified as:
Examples:
.. code-block:: nasm
.. parsed-literal::
offset = 30
s_branch loop_end

2
docs/AMDGPU/gfx8_msg.rst
View File

@ -60,7 +60,7 @@ Each message type supports specific operations:
Examples:
.. code-block:: nasm
.. parsed-literal::
s_sendmsg 0x12
s_sendmsg sendmsg(MSG_INTERRUPT)

2
docs/AMDGPU/gfx8_src_exp.rst
View File

@ -19,7 +19,7 @@ Data to copy to export buffers. This is an optional operand. Must be specified a
An example:
.. code-block:: nasm
.. parsed-literal::
exp mrtz v3, v3, off, off compr

2
docs/AMDGPU/gfx8_waitcnt.rst
View File

@ -44,7 +44,7 @@ These helpers may be specified in any order. Ampersands and commas may be used a
Examples:
.. code-block:: nasm
.. parsed-literal::
s_waitcnt 0
s_waitcnt vmcnt(1)

2
docs/AMDGPU/gfx9_attr.rst
View File

@ -23,7 +23,7 @@ Interpolation attribute and channel:
Examples:
.. code-block:: nasm
.. parsed-literal::
v_interp_p1_f32 v1, v0, attr0.x
v_interp_p1_f32 v1, v0, attr32.w

2
docs/AMDGPU/gfx9_hwreg.rst
View File

@ -52,7 +52,7 @@ Defined register *names* include:
Examples:
.. code-block:: nasm
.. parsed-literal::
s_getreg_b32 s2, 0x6
s_getreg_b32 s2, hwreg(15)

2
docs/AMDGPU/gfx9_label.rst
View File

@ -20,7 +20,7 @@ This operand may be specified as:
Examples:
.. code-block:: nasm
.. parsed-literal::
offset = 30
s_branch loop_end

2
docs/AMDGPU/gfx9_msg.rst
View File

@ -60,7 +60,7 @@ Each message type supports specific operations:
Examples:
.. code-block:: nasm
.. parsed-literal::
s_sendmsg 0x12
s_sendmsg sendmsg(MSG_INTERRUPT)

2
docs/AMDGPU/gfx9_src_exp.rst
View File

@ -19,7 +19,7 @@ Data to copy to export buffers. This is an optional operand. Must be specified a
An example:
.. code-block:: nasm
.. parsed-literal::
exp mrtz v3, v3, off, off compr

2
docs/AMDGPU/gfx9_waitcnt.rst
View File

@ -45,7 +45,7 @@ These helpers may be specified in any order. Ampersands and commas may be used a
Examples:
.. code-block:: nasm
.. parsed-literal::
s_waitcnt 0
s_waitcnt vmcnt(1)

2
docs/AMDGPUInstructionNotation.rst
View File

@ -81,7 +81,7 @@ Where:
Examples:
.. code-block:: nasm
.. parsed-literal::
src1:m // src1 operand may be used with operand modifiers
vdata:dst // vdata operand may be used as both source and destination

8
docs/AMDGPUInstructionSyntax.rst
View File

@ -90,21 +90,21 @@ The size of data is specified by size suffices:
Examples of instructions with different types of source and destination operands:
.. code-block:: nasm
.. parsed-literal::
s_bcnt0_i32_b64
v_cvt_f32_u32
Examples of instructions with one data type:
.. code-block:: nasm
.. parsed-literal::
v_max3_f32
v_max3_i16
Examples of instructions which operate with packed data:
.. code-block:: nasm
.. parsed-literal::
v_pk_add_u16
v_pk_add_i16
@ -112,7 +112,7 @@ Examples of instructions which operate with packed data:
Examples of typeless instructions which operate on b128 data:
.. code-block:: nasm
.. parsed-literal::
buffer_store_dwordx4
flat_load_dwordx4

42
docs/AMDGPUModifierSyntax.rst
View File

@ -43,7 +43,7 @@ Used with DS instructions which have 2 addresses.
Examples:
.. code-block:: nasm
.. parsed-literal::
offset:255
offset:0xff
@ -66,7 +66,7 @@ Used with DS instructions which have 1 address.
Examples:
.. code-block:: nasm
.. parsed-literal::
offset:65535
offset:0xffff
@ -133,7 +133,7 @@ Numeric parameters may be specified as either :ref:`integer numbers<amdgpu_synid
Examples:
.. code-block:: nasm
.. parsed-literal::
offset:255
offset:0xffff
@ -221,7 +221,7 @@ Cannot be used with *global/scratch* opcodes. GFX9 only.
Examples:
.. code-block:: nasm
.. parsed-literal::
offset:4095
offset:0xff
@ -244,7 +244,7 @@ Can be used with *global/scratch* opcodes only. GFX9 only.
Examples:
.. code-block:: nasm
.. parsed-literal::
offset:-4000
offset:0x10
@ -309,7 +309,7 @@ This modifier has some limitations depending on instruction kind:
Examples:
.. code-block:: nasm
.. parsed-literal::
dmask:0xf
dmask:0b1111
@ -559,7 +559,7 @@ Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
Examples:
.. code-block:: nasm
.. parsed-literal::
offset:0
offset:0x10
@ -674,7 +674,7 @@ Note: Numeric parameters may be specified as either
Examples:
.. code-block:: nasm
.. parsed-literal::
quad_perm:[0, 1, 2, 3]
row_shl:3
@ -700,7 +700,7 @@ Note. The lanes of a wavefront are organized in four banks and four rows.
Examples:
.. code-block:: nasm
.. parsed-literal::
row_mask:0xf
row_mask:0b1010
@ -727,7 +727,7 @@ Note. The lanes of a wavefront are organized in four banks and four rows.
Examples:
.. code-block:: nasm
.. parsed-literal::
bank_mask:0x3
bank_mask:0b0011
@ -879,7 +879,7 @@ Valid for integer operands only.
Examples:
.. code-block:: nasm
.. parsed-literal::
sext(v4)
sext(v255)
@ -915,7 +915,7 @@ GFX9 only.
Examples:
.. code-block:: nasm
.. parsed-literal::
op_sel:[0,0]
op_sel:[0,1]
@ -994,10 +994,10 @@ Valid for floating point operands only.
Examples:
.. code-block:: nasm
.. parsed-literal::
abs(v36)
|v36|
\|v36|
.. _amdgpu_synid_neg:
@ -1016,7 +1016,7 @@ Valid for floating point operands only.
Examples:
.. code-block:: nasm
.. parsed-literal::
neg(v[0])
-v4
@ -1055,7 +1055,7 @@ The value 0 selects the low bits, while 1 selects the high bits.
Examples:
.. code-block:: nasm
.. parsed-literal::
op_sel:[0,0]
op_sel:[0,1,0]
@ -1084,7 +1084,7 @@ The value 0 selects the low bits, while 1 selects the high bits.
Examples:
.. code-block:: nasm
.. parsed-literal::
op_sel_hi:[0,0]
op_sel_hi:[0,0,1]
@ -1118,7 +1118,7 @@ This modifier is valid for floating point operands only.
Examples:
.. code-block:: nasm
.. parsed-literal::
neg_lo:[0]
neg_lo:[0,1]
@ -1152,7 +1152,7 @@ This modifier is valid for floating point operands only.
Examples:
.. code-block:: nasm
.. parsed-literal::
neg_hi:[1,0]
neg_hi:[0,1,1]
@ -1200,7 +1200,7 @@ By default, low bits are used for all operands.
Examples:
.. code-block:: nasm
.. parsed-literal::
op_sel:[0,1]
@ -1228,7 +1228,7 @@ The location of 16 bits in the operand may be specified by
Examples:
.. code-block:: nasm
.. parsed-literal::
op_sel_hi:[1,1,1]

34
docs/AMDGPUOperandSyntax.rst
View File

@ -63,7 +63,7 @@ Note. *N* and *K* must satisfy the following conditions:
Examples:
.. code-block:: nasm
.. parsed-literal::
v255
v[0]
@ -127,7 +127,7 @@ Note. *N* and *K* must satisfy the following conditions:
Examples:
.. code-block:: nasm
.. parsed-literal::
s0
s[0]
@ -141,7 +141,7 @@ Examples:
Examples of *scalar* registers with an invalid alignment:
.. code-block:: nasm
.. parsed-literal::
s[1:2]
s[2:5]
@ -210,7 +210,7 @@ Note. *N* and *K* must satisfy the following conditions:
Examples:
.. code-block:: nasm
.. parsed-literal::
ttmp0
ttmp[0]
@ -224,7 +224,7 @@ Examples:
Examples of *ttmp* registers with an invalid alignment:
.. code-block:: nasm
.. parsed-literal::
ttmp[1:2]
ttmp[2:5]
@ -645,7 +645,7 @@ They may be specified in binary, octal, hexadecimal and decimal formats:
Examples:
.. code-block:: nasm
.. parsed-literal::
-1234
0b1010
@ -671,7 +671,7 @@ Floating-point numbers may be specified in hexadecimal and decimal formats:
Examples:
.. code-block:: nasm
.. parsed-literal::
-1.234
234e2
@ -700,7 +700,7 @@ such as labels.
Examples:
.. code-block:: nasm
.. parsed-literal::
x = -1
y = x + 10
@ -719,7 +719,7 @@ Addition information about relocation may be found :ref:`here<amdgpu-relocation-
Examples:
.. code-block:: nasm
.. parsed-literal::
y = x + 10 // x is not yet defined. Undefined symbols are assumed to be PC-relative.
z = .
@ -736,7 +736,7 @@ No conversion from floating-point to integer is performed.
Examples:
.. code-block:: nasm
.. parsed-literal::
x = 0.1 // x is assigned an integer 4591870180066957722 which is a binary representation of 0.1.
y = x + x // y is a sum of two integer values; it is not equal to 0.2!
@ -897,7 +897,7 @@ No data type conversions are performed.
Examples:
.. code-block:: nasm
.. parsed-literal::
// GFX9
@ -920,7 +920,7 @@ when used as operands they are converted to a floating-point number of
Examples:
.. code-block:: nasm
.. parsed-literal::
// GFX9
@ -969,7 +969,7 @@ There are two cases when the conversion is possible:
Examples of valid literals:
.. code-block:: nasm
.. parsed-literal::
// GFX9
@ -983,7 +983,7 @@ Examples of valid literals:
Examples of invalid literals:
.. code-block:: nasm
.. parsed-literal::
// GFX9
@ -1021,7 +1021,7 @@ Precision lost is allowed.
Examples of valid literals:
.. code-block:: nasm
.. parsed-literal::
// GFX9
@ -1033,7 +1033,7 @@ Examples of valid literals:
Examples of invalid literals:
.. code-block:: nasm
.. parsed-literal::
// GFX9
@ -1052,7 +1052,7 @@ No data type conversions are performed.
Examples:
.. code-block:: nasm
.. parsed-literal::
// GFX9