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Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:
- cfi directives are not inserted at the right location or in the right order. - The source MachineLocation for the cfi directive that changes the cfa register to $fp should be MachineLocation::VirtualFP. - A PROLOG_LABEL that marks the beginning of cfi_offset directives for callee-saved register is emitted even when no callee-saved registers are saved. - When a callee-saved double precision register is saved, two cfi_offset directives, one for each of the paired single precision registers, should be emitted. llvm-svn: 132703
This commit is contained in:
Akira Hatanaka
parent
6575812c48
commit
fbeb14925f
@ -173,6 +173,10 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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MachineModuleInfo &MMI = MF.getMMI();
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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MachineLocation DstML, SrcML;
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// Adjust stack : addi sp, sp, (-imm)
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ATUsed = expandRegLargeImmPair(Mips::SP, -StackSize, NewReg, NewImm, MBB,
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MBBI);
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@ -183,49 +187,75 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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if (ATUsed)
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
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// emit ".cfi_def_cfa_offset StackSize"
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MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
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DstML = MachineLocation(MachineLocation::VirtualFP);
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SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
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Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
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// Find the instruction past the last instruction that saves a callee-saved
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// register to the stack.
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.size()) {
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for (unsigned i = 0; i < CSI.size(); ++i)
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++MBBI;
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// Iterate over list of callee-saved registers and emit .cfi_offset directives.
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MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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// If Reg is a double precision register, emit two cfa_offsets,
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// one for each of the paired single precision registers.
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if (Mips::AFGR64RegisterClass->contains(Reg)) {
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const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
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MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
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MachineLocation SrcML0(*SubRegs);
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MachineLocation SrcML1(*(SubRegs + 1));
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if (!STI.isLittle())
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std::swap(SrcML0, SrcML1);
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Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
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Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
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}
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else {
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// Reg is either in CPURegs or FGR32.
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DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
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SrcML = MachineLocation(Reg);
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Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
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}
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}
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}
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// if framepointer enabled, set it to point to the stack pointer.
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if (hasFP(MF))
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if (hasFP(MF)) {
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// Insert instruction "move $fp, $sp" at this location.
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BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
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.addReg(Mips::SP).addReg(Mips::ZERO);
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// emit ".cfi_def_cfa_register $fp"
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MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
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DstML = MachineLocation(Mips::FP);
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SrcML = MachineLocation(MachineLocation::VirtualFP);
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Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
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}
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// Restore GP from the saved stack location
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if (MipsFI->needGPSaveRestore())
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BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
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.addImm(MFI->getObjectOffset(MipsFI->getGPFI()));
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// EH Frame infomation.
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MachineModuleInfo &MMI = MF.getMMI();
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL)).addSym(FrameLabel);
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if (hasFP(MF)) {
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MachineLocation SPDst(Mips::FP);
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MachineLocation SPSrc(Mips::SP);
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Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
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}
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if (StackSize) {
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MachineLocation SPDst(MachineLocation::VirtualFP);
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MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize);
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Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
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}
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
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MachineLocation CSSrc(I->getReg());
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Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc));
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}
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}
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void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
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78
test/CodeGen/Mips/eh.ll
Normal file
78
test/CodeGen/Mips/eh.ll
Normal file
@ -0,0 +1,78 @@
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; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL
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; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB
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@g1 = global double 0.000000e+00, align 8
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@_ZTId = external constant i8*
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define void @_Z1fd(double %i2) {
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entry:
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; CHECK-EL: addiu $sp, $sp
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; CHECK-EL: .cfi_def_cfa_offset
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; CHECK-EL: sdc1 $f20
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; CHECK-EL: sw $ra
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; CHECK-EL: sw $17
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; CHECK-EL: sw $16
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; CHECK-EL: .cfi_offset 52, -8
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; CHECK-EL: .cfi_offset 53, -4
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; CHECK-EB: .cfi_offset 53, -8
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; CHECK-EB: .cfi_offset 52, -4
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; CHECK-EL: .cfi_offset 31, -12
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; CHECK-EL: .cfi_offset 17, -16
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; CHECK-EL: .cfi_offset 16, -20
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; CHECK-EL: .cprestore
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%exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind
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%0 = bitcast i8* %exception to double*
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store double 3.200000e+00, double* %0, align 8, !tbaa !0
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invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTId to i8*), i8* null) noreturn
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to label %unreachable unwind label %lpad
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lpad: ; preds = %entry
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; CHECK-EL: # %lpad
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; CHECK-EL: lw $gp
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; CHECK-EL: beq $5
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%exn = tail call i8* @llvm.eh.exception() nounwind
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%eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTId to i8*)) nounwind
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%1 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTId to i8*)) nounwind
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%2 = icmp eq i32 %eh.selector, %1
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br i1 %2, label %catch, label %eh.resume
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catch: ; preds = %lpad
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%3 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind
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%4 = bitcast i8* %3 to double*
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%exn.scalar = load double* %4, align 8
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%add = fadd double %exn.scalar, %i2
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store double %add, double* @g1, align 8, !tbaa !0
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tail call void @__cxa_end_catch() nounwind
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ret void
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eh.resume: ; preds = %lpad
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tail call void @llvm.eh.resume(i8* %exn, i32 %eh.selector) noreturn
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unreachable
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unreachable: ; preds = %entry
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unreachable
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}
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declare i8* @__cxa_allocate_exception(i32)
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declare i8* @llvm.eh.exception() nounwind readonly
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declare i32 @__gxx_personality_v0(...)
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declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind
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declare i32 @llvm.eh.typeid.for(i8*) nounwind
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declare void @llvm.eh.resume(i8*, i32)
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declare void @__cxa_throw(i8*, i8*, i8*)
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declare i8* @__cxa_begin_catch(i8*)
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declare void @__cxa_end_catch()
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!0 = metadata !{metadata !"double", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
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