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Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.
llvm-svn: 55925
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@ -107,7 +107,8 @@ private:
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};
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static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT) {
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static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT,
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bool AllowI1 = false) {
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VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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@ -119,7 +120,7 @@ static bool isTypeLegal(const Type *Ty, const TargetLowering &TLI, MVT &VT) {
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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return TLI.isTypeLegal(VT);
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return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
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}
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#include "X86GenCallingConv.inc"
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@ -701,9 +702,16 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
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// Handle *simple* calls for now.
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const Type *RetTy = CS.getType();
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MVT RetVT;
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if (!isTypeLegal(RetTy, TLI, RetVT))
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if (!isTypeLegal(RetTy, TLI, RetVT, true))
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return false;
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// Allow calls which produce i1 results.
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bool AndToI1 = false;
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if (RetVT == MVT::i1) {
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RetVT = MVT::i8;
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AndToI1 = true;
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}
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// Deal with call operands first.
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SmallVector<unsigned, 4> Args;
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SmallVector<MVT, 4> ArgVTs;
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@ -859,6 +867,13 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
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addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
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}
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if (AndToI1) {
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// Mask out all but lowest bit for some call which produces an i1.
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unsigned AndResult = createResultReg(X86::GR8RegisterClass);
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BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
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ResultReg = AndResult;
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}
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UpdateValueMap(I, ResultReg);
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}
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13
test/CodeGen/X86/fast-isel-call.ll
Normal file
13
test/CodeGen/X86/fast-isel-call.ll
Normal file
@ -0,0 +1,13 @@
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; RUN: llvm-as < %s | llc -fast-isel -march=x86 | grep and
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define i32 @t() nounwind {
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tak:
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%tmp = call i1 @foo()
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br i1 %tmp, label %BB1, label %BB2
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BB1:
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ret i32 1
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BB2:
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ret i32 0
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}
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declare i1 @foo() zeroext nounwind
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