[AVX-512] Remove COPY_TO_REGCLASS from a few patterns that already had the correct register class.

llvm-svn: 281860
This commit is contained in:
Craig Topper 2016-09-18 18:59:33 +00:00
parent ca3730b14d
commit fca6198042

View File

@ -5589,13 +5589,13 @@ defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info,
// Therefore, the SSE intrinsics are mapped to the AVX512 instructions.
let Predicates = [HasAVX512] in {
def : Pat<(i32 (int_x86_sse_cvtss2si (v4f32 VR128X:$src))),
(VCVTSS2SIZrr (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
(VCVTSS2SIZrr VR128X:$src)>;
def : Pat<(i64 (int_x86_sse_cvtss2si64 (v4f32 VR128X:$src))),
(VCVTSS2SI64Zrr (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
(VCVTSS2SI64Zrr VR128X:$src)>;
def : Pat<(i32 (int_x86_sse2_cvtsd2si (v2f64 VR128X:$src))),
(VCVTSD2SIZrr (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
(VCVTSD2SIZrr VR128X:$src)>;
def : Pat<(i64 (int_x86_sse2_cvtsd2si64 (v2f64 VR128X:$src))),
(VCVTSD2SI64Zrr (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
(VCVTSD2SI64Zrr VR128X:$src)>;
} // HasAVX512
let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
@ -5690,13 +5690,13 @@ defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i64x_info,
XD, VEX_W, EVEX_CD8<64, CD8VT1>;
let Predicates = [HasAVX512] in {
def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
(VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
(VCVTTSS2SIZrr_Int VR128X:$src)>;
def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
(VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
(VCVTTSS2SI64Zrr_Int VR128X:$src)>;
def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
(VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
(VCVTTSD2SIZrr_Int VR128X:$src)>;
def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
(VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
(VCVTTSD2SI64Zrr_Int VR128X:$src)>;
} // HasAVX512
//===----------------------------------------------------------------------===//