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[AArch64] Split zero cycle feature more granularly
Split the `zcz` feature into specific ones got GP and FP registers, `zcz-gp` and `zcz-fp`, respectively, while retaining the original feature option to mean both. Differential revision: https://reviews.llvm.org/D52621 llvm-svn: 343354
This commit is contained in:
Evandro Menezes
parent
882252baeb
commit
fdd7b1d490
@ -80,13 +80,17 @@ def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
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def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
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"Enable Scalable Vector Extension (SVE) instructions">;
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/// Cyclone has register move instructions which are "free".
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def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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"Has zero-cycle register moves">;
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def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
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"Has zero-cycle zeroing instructions for generic registers">;
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def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
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"Has zero-cycle zeroing instructions for FP registers">;
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/// Cyclone has instructions which zero registers for "free".
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions">;
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"Has zero-cycle zeroing instructions",
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[FeatureZCZeroingGP, FeatureZCZeroingFP]>;
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/// ... but the floating-point version doesn't quite work in rare cases on older
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/// CPUs.
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@ -404,7 +408,7 @@ def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
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FeaturePostRAScheduler,
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FeatureSlowMisaligned128Store,
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FeatureUseRSqrt,
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FeatureZCZeroing]>;
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FeatureZCZeroingFP]>;
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def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
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"Samsung Exynos-M2 processors",
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@ -418,7 +422,7 @@ def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeatureSlowMisaligned128Store,
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FeatureZCZeroing]>;
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FeatureZCZeroingFP]>;
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def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
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"Samsung Exynos-M3 processors",
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@ -435,7 +439,7 @@ def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
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FeaturePerfMon,
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FeaturePostRAScheduler,
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FeaturePredictableSelectIsExpensive,
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FeatureZCZeroing]>;
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FeatureZCZeroingFP]>;
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def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
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"Qualcomm Kryo processors", [
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@ -503,7 +503,7 @@ void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
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void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
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unsigned DestReg = MI.getOperand(0).getReg();
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if (STI->hasZeroCycleZeroing() && !STI->hasZeroCycleZeroingFPWorkaround()) {
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if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround()) {
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// Convert H/S/D register to corresponding Q register
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if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
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DestReg = AArch64::Q0 + (DestReg - AArch64::H0);
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@ -729,9 +729,9 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
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case AArch64::FMOVH0:
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case AArch64::FMOVS0:
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case AArch64::FMOVD0:
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return Subtarget.hasZeroCycleZeroing();
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return Subtarget.hasZeroCycleZeroingFP();
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case TargetOpcode::COPY:
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return (Subtarget.hasZeroCycleZeroing() &&
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return (Subtarget.hasZeroCycleZeroingGP() &&
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(MI.getOperand(1).getReg() == AArch64::WZR ||
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MI.getOperand(1).getReg() == AArch64::XZR));
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}
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@ -2481,7 +2481,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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.addImm(0)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
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}
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} else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroing()) {
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} else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGP()) {
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BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
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.addImm(0)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
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@ -2518,7 +2518,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addImm(0)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
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} else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroing()) {
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} else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGP()) {
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BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
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.addImm(0)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
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@ -109,6 +109,8 @@ protected:
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// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
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bool HasZeroCycleZeroing = false;
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bool HasZeroCycleZeroingGP = false;
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bool HasZeroCycleZeroingFP = false;
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bool HasZeroCycleZeroingFPWorkaround = false;
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// StrictAlign - Disallow unaligned memory accesses.
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@ -228,7 +230,9 @@ public:
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bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
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bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
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bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
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bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
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bool hasZeroCycleZeroingFPWorkaround() const {
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return HasZeroCycleZeroingFPWorkaround;
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@ -1,16 +1,20 @@
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
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; rdar://12254953
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; RUN: llc < %s -mtriple=arm64-apple-ios -mattr=-zcm | FileCheck %s -check-prefixes=CHECK,NOT
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; RUN: llc < %s -mtriple=arm64-apple-ios -mattr=+zcm | FileCheck %s -check-prefixes=CHECK,YES
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; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=CHECK,YES
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; rdar://12254953
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define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind ssp {
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entry:
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; CHECK-LABEL: t:
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; CHECK: mov [[REG2:x[0-9]+]], x3
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; CHECK: mov [[REG1:x[0-9]+]], x2
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; CHECK: mov x0, x2
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; CHECK: mov x1, x3
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; NOT: mov [[REG2:w[0-9]+]], w3
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; NOT: mov [[REG1:w[0-9]+]], w2
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; YES: mov [[REG2:x[0-9]+]], x3
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; YES: mov [[REG1:x[0-9]+]], x2
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; CHECK: bl _foo
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; CHECK: mov x0, [[REG1]]
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; CHECK: mov x1, [[REG2]]
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; NOT: mov w0, [[REG1]]
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; NOT: mov w1, [[REG2]]
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; YES: mov x0, [[REG1]]
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; YES: mov x1, [[REG2]]
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%call = call i32 @foo(i32 %c, i32 %d) nounwind
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%call1 = call i32 @foo(i32 %c, i32 %d) nounwind
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unreachable
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@ -1,9 +1,14 @@
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefixes=ALL,CYCLONE
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone -mattr=+fullfp16 < %s | FileCheck %s -check-prefixes=CYCLONE-FULLFP16
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m1 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m3 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=-zcz | FileCheck %s -check-prefixes=ALL,NONEGP,NONEFP
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz -mattr=+fullfp16 | FileCheck %s -check-prefixes=ALL,ZEROGP,ZERO16
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gp | FileCheck %s -check-prefixes=ALL,ZEROGP,NONEFP
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-fp | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
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; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,ZEROGP,NONEFP
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; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone -mattr=+fullfp16 | FileCheck %s -check-prefixes=ALL,ZEROGP,NONE16
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
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declare void @bar(half, float, double, <2 x double>)
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declare void @bari(i32, i32)
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@ -14,17 +19,22 @@ define void @t1() nounwind ssp {
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entry:
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; ALL-LABEL: t1:
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; ALL-NOT: fmov
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; ALL: ldr h0,{{.*}}
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; CYCLONE: fmov s1, wzr
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; CYCLONE: fmov d2, xzr
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; CYCLONE: movi.16b v3, #0
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; CYCLONE-FULLFP16: fmov h0, wzr
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; CYCLONE-FULLFP16: fmov s1, wzr
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; CYCLONE-FULLFP16: fmov d2, xzr
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; CYCLONE-FULLFP16: movi.16b v3, #0
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; NONEFP: ldr h0,{{.*}}
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; NONEFP: fmov s1, wzr
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; NONEFP: fmov d2, xzr
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; NONEFP: movi{{(.16b)?}} v3{{(.2d)?}}, #0
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; NONE16: fmov h0, wzr
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; NONE16: fmov s1, wzr
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; NONE16: fmov d2, xzr
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; NONE16: movi{{(.16b)?}} v3{{(.2d)?}}, #0
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; ZEROFP: ldr h0,{{.*}}
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; ZEROFP: movi v{{[0-3]+}}.2d, #0
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; ZEROFP: movi v{{[0-3]+}}.2d, #0
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; ZEROFP: movi v{{[0-3]+}}.2d, #0
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; ZERO16: movi v{{[0-3]+}}.2d, #0
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; ZERO16: movi v{{[0-3]+}}.2d, #0
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; ZERO16: movi v{{[0-3]+}}.2d, #0
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; ZERO16: movi v{{[0-3]+}}.2d, #0
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tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind
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ret void
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}
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@ -32,9 +42,10 @@ entry:
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define void @t2() nounwind ssp {
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entry:
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; ALL-LABEL: t2:
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; ALL-NOT: mov w0, wzr
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; ALL: mov w{{[0-3]+}}, #0
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; ALL: mov w{{[0-3]+}}, #0
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; NONEGP: mov w0, wzr
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; NONEGP: mov w1, wzr
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; ZEROGP: mov w0, #0
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; ZEROGP: mov w1, #0
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tail call void @bari(i32 0, i32 0) nounwind
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ret void
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}
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@ -42,26 +53,26 @@ entry:
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define void @t3() nounwind ssp {
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entry:
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; ALL-LABEL: t3:
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; ALL-NOT: mov x0, xzr
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; ALL: mov x{{[0-3]+}}, #0
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; ALL: mov x{{[0-3]+}}, #0
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; NONEGP: mov x0, xzr
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; NONEGP: mov x1, xzr
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; ZEROGP: mov x0, #0
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; ZEROGP: mov x1, #0
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tail call void @barl(i64 0, i64 0) nounwind
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ret void
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}
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define void @t4() nounwind ssp {
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; ALL-LABEL: t4:
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; ALL-NOT: fmov
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; CYCLONE: fmov s{{[0-3]+}}, wzr
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; CYCLONE: fmov s{{[0-3]+}}, wzr
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; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
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; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; NONEFP: fmov s{{[0-3]+}}, wzr
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; NONEFP: fmov s{{[0-3]+}}, wzr
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; ZEROFP: movi v{{[0-3]+}}.2d, #0
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; ZEROFP: movi v{{[0-3]+}}.2d, #0
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tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
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ret void
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}
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declare double @sin(double)
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; We used to produce spills+reloads for a Q register with zero cycle zeroing
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; enabled.
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; ALL-LABEL: foo:
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@ -88,10 +99,133 @@ for.end:
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define <2 x i64> @t6() {
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; ALL-LABEL: t6:
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; CYCLONE: movi.16b v0, #0
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; OTHERS: movi v0.2d, #0000000000000000
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ret <2 x i64> zeroinitializer
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; ALL: movi{{(.16b)?}} v0{{(.2d)?}}, #0
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ret <2 x i64> zeroinitializer
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}
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define i1 @ti1() {
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entry:
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; ALL-LABEL: ti1:
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; NONEGP: mov w0, wzr
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; ZEROGP: mov w0, #0
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ret i1 false
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}
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define i8 @ti8() {
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entry:
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; ALL-LABEL: ti8:
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; NONEGP: mov w0, wzr
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; ZEROGP: mov w0, #0
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ret i8 0
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}
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define i16 @ti16() {
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entry:
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; ALL-LABEL: ti16:
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; NONEGP: mov w0, wzr
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; ZEROGP: mov w0, #0
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ret i16 0
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}
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define i32 @ti32() {
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entry:
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; ALL-LABEL: ti32:
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; NONEGP: mov w0, wzr
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; ZEROGP: mov w0, #0
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ret i32 0
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}
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define i64 @ti64() {
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entry:
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; ALL-LABEL: ti64:
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; NONEGP: mov x0, xzr
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; ZEROGP: mov x0, #0
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ret i64 0
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}
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define float @tf32() {
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entry:
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; ALL-LABEL: tf32:
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; NONEFP: mov s0, wzr
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; ZEROFP: movi v0.2d, #0
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ret float 0.0
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}
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define double @td64() {
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entry:
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; ALL-LABEL: td64:
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; NONEFP: mov d0, xzr
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; ZEROFP: movi v0.2d, #0
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ret double 0.0
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}
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define <8 x i8> @tv8i8() {
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entry:
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; ALL-LABEL: tv8i8:
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; ALL: movi d0, #0
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ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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}
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define <4 x i16> @tv4i16() {
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entry:
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; ALL-LABEL: tv4i16:
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; ALL: movi d0, #0
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ret <4 x i16> <i16 0, i16 0, i16 0, i16 0>
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}
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define <2 x i32> @tv2i32() {
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entry:
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; ALL-LABEL: tv2i32:
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; ALL: movi d0, #0
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ret <2 x i32> <i32 0, i32 0>
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}
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define <2 x float> @tv2f32() {
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entry:
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; ALL-LABEL: tv2f32:
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; ALL: movi d0, #0
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ret <2 x float> <float 0.0, float 0.0>
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}
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define <16 x i8> @tv16i8() {
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entry:
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; ALL-LABEL: tv16i8:
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; ALL: movi{{(.16b)?}} v0{{(.2d)?}}, #0
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ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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}
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define <8 x i16> @tv8i16() {
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entry:
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; ALL-LABEL: tv8i16:
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; ALL: movi{{(.16b)?}} v0{{(.2d)?}}, #0
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ret <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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}
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define <4 x i32> @tv4i32() {
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entry:
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||||
; ALL-LABEL: tv4i32:
|
||||
; ALL: movi{{(.16b)?}} v0{{(.2d)?}}, #0
|
||||
ret <4 x i32> <i32 0, i32 0, i32 0, i32 0>
|
||||
}
|
||||
|
||||
define <2 x i64> @tv2i64() {
|
||||
entry:
|
||||
; ALL-LABEL: tv2i64:
|
||||
; ALL: movi{{(.16b)?}} v0{{(.2d)?}}, #0
|
||||
ret <2 x i64> <i64 0, i64 0>
|
||||
}
|
||||
|
||||
define <4 x float> @tv4f32() {
|
||||
entry:
|
||||
; ALL-LABEL: tv4f32:
|
||||
; ALL: movi{{(.16b)?}} v0{{(.2d)?}}, #0
|
||||
ret <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
|
||||
}
|
||||
|
||||
define <2 x double> @tv2d64() {
|
||||
entry:
|
||||
; ALL-LABEL: tv2d64:
|
||||
; ALL: movi{{(.16b)?}} v0{{(.2d)?}}, #0
|
||||
ret <2 x double> <double 0.0, double 0.0>
|
||||
}
|
||||
|
||||
declare double @sin(double)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user