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Oops. Didn't mean to check in a quick hack.

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llvm-svn: 36227
This commit is contained in:
Evan Cheng 2007-04-17 23:33:39 +00:00
parent 1677782ef0
commit fe5856c4f3
1 changed files with 16 additions and 8 deletions
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24
lib/Target/MRegisterInfo.cpp
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@ -34,18 +34,26 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
MRegisterInfo::~MRegisterInfo() {}
/// getAllocatableSetForRC - Toggle the bits that represent allocatable
/// registers for the specific register class.
static void getAllocatableSetForRC(MachineFunction &MF,
const TargetRegisterClass *RC, BitVector &R){
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I)
R.set(*I);
}
BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
const TargetRegisterClass *RC) const {
BitVector Allocatable(NumRegs);
for (MRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I) {
const TargetRegisterClass *TRC = *I;
if (RC && TRC != RC)
continue;
for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(MF),
E = TRC->allocation_order_end(MF); I != E; ++I)
Allocatable.set(*I);
if (RC) {
getAllocatableSetForRC(MF, RC, Allocatable);
return Allocatable;
}
for (MRegisterInfo::regclass_iterator I = regclass_begin(),
E = regclass_end(); I != E; ++I)
getAllocatableSetForRC(MF, *I, Allocatable);
return Allocatable;
}