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Masked Load and Store Intrinsics in loop vectorizer.
The loop vectorizer optimizes loops containing conditional memory accesses by generating masked load and store intrinsics. This decision is target dependent. http://reviews.llvm.org/D6527 llvm-svn: 224334
This commit is contained in:
Elena Demikhovsky
parent
018d1acab3
commit
fe73fcc29b
@ -580,9 +580,10 @@ public:
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LoopVectorizationLegality(Loop *L, ScalarEvolution *SE, const DataLayout *DL,
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DominatorTree *DT, TargetLibraryInfo *TLI,
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AliasAnalysis *AA, Function *F)
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AliasAnalysis *AA, Function *F,
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const TargetTransformInfo *TTI)
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: NumLoads(0), NumStores(0), NumPredStores(0), TheLoop(L), SE(SE), DL(DL),
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DT(DT), TLI(TLI), AA(AA), TheFunction(F), Induction(nullptr),
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DT(DT), TLI(TLI), AA(AA), TheFunction(F), TTI(TTI), Induction(nullptr),
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WidestIndTy(nullptr), HasFunNoNaNAttr(false), MaxSafeDepDistBytes(-1U) {
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}
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@ -768,6 +769,21 @@ public:
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}
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SmallPtrSet<Value *, 8>::iterator strides_end() { return StrideSet.end(); }
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/// Returns true if the target machine supports masked store operation
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/// for the given \p DataType and kind of access to \p Ptr.
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bool isLegalMaskedStore(Type *DataType, Value *Ptr) {
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return TTI->isLegalMaskedStore(DataType, isConsecutivePtr(Ptr));
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}
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/// Returns true if the target machine supports masked load operation
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/// for the given \p DataType and kind of access to \p Ptr.
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bool isLegalMaskedLoad(Type *DataType, Value *Ptr) {
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return TTI->isLegalMaskedLoad(DataType, isConsecutivePtr(Ptr));
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}
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/// Returns true if vector representation of the instruction \p I
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/// requires mask.
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bool isMaskRequired(const Instruction* I) {
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return (MaskedOp.count(I) != 0);
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}
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private:
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/// Check if a single basic block loop is vectorizable.
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/// At this point we know that this is a loop with a constant trip count
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@ -840,6 +856,8 @@ private:
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AliasAnalysis *AA;
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/// Parent function
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Function *TheFunction;
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/// Target Transform Info
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const TargetTransformInfo *TTI;
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// --- vectorization state --- //
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@ -871,6 +889,10 @@ private:
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ValueToValueMap Strides;
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SmallPtrSet<Value *, 8> StrideSet;
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/// While vectorizing these instructions we have to generate a
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/// call to the appropriate masked intrinsic
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SmallPtrSet<const Instruction*, 8> MaskedOp;
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};
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/// LoopVectorizationCostModel - estimates the expected speedups due to
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@ -1373,7 +1395,7 @@ struct LoopVectorize : public FunctionPass {
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}
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// Check if it is legal to vectorize the loop.
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LoopVectorizationLegality LVL(L, SE, DL, DT, TLI, AA, F);
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LoopVectorizationLegality LVL(L, SE, DL, DT, TLI, AA, F, TTI);
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if (!LVL.canVectorize()) {
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DEBUG(dbgs() << "LV: Not vectorizing: Cannot prove legality.\n");
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emitMissedWarning(F, L, Hints);
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@ -1761,7 +1783,8 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction(Instruction *Instr) {
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unsigned ScalarAllocatedSize = DL->getTypeAllocSize(ScalarDataTy);
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unsigned VectorElementSize = DL->getTypeStoreSize(DataTy)/VF;
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if (SI && Legal->blockNeedsPredication(SI->getParent()))
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if (SI && Legal->blockNeedsPredication(SI->getParent()) &&
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!Legal->isMaskRequired(SI))
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return scalarizeInstruction(Instr, true);
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if (ScalarAllocatedSize != VectorElementSize)
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@ -1855,8 +1878,24 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction(Instruction *Instr) {
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Value *VecPtr = Builder.CreateBitCast(PartPtr,
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DataTy->getPointerTo(AddressSpace));
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StoreInst *NewSI =
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Builder.CreateAlignedStore(StoredVal[Part], VecPtr, Alignment);
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Instruction *NewSI;
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if (Legal->isMaskRequired(SI)) {
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Type *I8PtrTy =
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Builder.getInt8PtrTy(PartPtr->getType()->getPointerAddressSpace());
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Value *I8Ptr = Builder.CreateBitCast(PartPtr, I8PtrTy);
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VectorParts Cond = createBlockInMask(SI->getParent());
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SmallVector <Value *, 8> Ops;
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Ops.push_back(I8Ptr);
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Ops.push_back(StoredVal[Part]);
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Ops.push_back(Builder.getInt32(Alignment));
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Ops.push_back(Cond[Part]);
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NewSI = Builder.CreateMaskedStore(Ops);
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}
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else
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NewSI = Builder.CreateAlignedStore(StoredVal[Part], VecPtr, Alignment);
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propagateMetadata(NewSI, SI);
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}
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return;
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@ -1876,9 +1915,26 @@ void InnerLoopVectorizer::vectorizeMemoryInstruction(Instruction *Instr) {
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PartPtr = Builder.CreateGEP(PartPtr, Builder.getInt32(1 - VF));
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}
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Value *VecPtr = Builder.CreateBitCast(PartPtr,
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DataTy->getPointerTo(AddressSpace));
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LoadInst *NewLI = Builder.CreateAlignedLoad(VecPtr, Alignment, "wide.load");
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Instruction* NewLI;
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if (Legal->isMaskRequired(LI)) {
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Type *I8PtrTy =
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Builder.getInt8PtrTy(PartPtr->getType()->getPointerAddressSpace());
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Value *I8Ptr = Builder.CreateBitCast(PartPtr, I8PtrTy);
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VectorParts SrcMask = createBlockInMask(LI->getParent());
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SmallVector <Value *, 8> Ops;
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Ops.push_back(I8Ptr);
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Ops.push_back(UndefValue::get(DataTy));
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Ops.push_back(Builder.getInt32(Alignment));
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Ops.push_back(SrcMask[Part]);
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NewLI = Builder.CreateMaskedLoad(Ops);
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}
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else {
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Value *VecPtr = Builder.CreateBitCast(PartPtr,
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DataTy->getPointerTo(AddressSpace));
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NewLI = Builder.CreateAlignedLoad(VecPtr, Alignment, "wide.load");
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}
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propagateMetadata(NewLI, LI);
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Entry[Part] = Reverse ? reverseVector(NewLI) : NewLI;
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}
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@ -5305,27 +5361,8 @@ bool LoopVectorizationLegality::blockNeedsPredication(BasicBlock *BB) {
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bool LoopVectorizationLegality::blockCanBePredicated(BasicBlock *BB,
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SmallPtrSetImpl<Value *> &SafePtrs) {
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for (BasicBlock::iterator it = BB->begin(), e = BB->end(); it != e; ++it) {
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// We might be able to hoist the load.
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if (it->mayReadFromMemory()) {
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LoadInst *LI = dyn_cast<LoadInst>(it);
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if (!LI || !SafePtrs.count(LI->getPointerOperand()))
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return false;
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}
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// We don't predicate stores at the moment.
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if (it->mayWriteToMemory()) {
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StoreInst *SI = dyn_cast<StoreInst>(it);
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// We only support predication of stores in basic blocks with one
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// predecessor.
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if (!SI || ++NumPredStores > NumberOfStoresToPredicate ||
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!SafePtrs.count(SI->getPointerOperand()) ||
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!SI->getParent()->getSinglePredecessor())
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return false;
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}
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if (it->mayThrow())
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return false;
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// Check that we don't have a constant expression that can trap as operand.
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for (Instruction::op_iterator OI = it->op_begin(), OE = it->op_end();
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OI != OE; ++OI) {
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@ -5333,6 +5370,48 @@ bool LoopVectorizationLegality::blockCanBePredicated(BasicBlock *BB,
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if (C->canTrap())
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return false;
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}
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// We might be able to hoist the load.
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if (it->mayReadFromMemory()) {
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LoadInst *LI = dyn_cast<LoadInst>(it);
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if (!LI)
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return false;
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if (!SafePtrs.count(LI->getPointerOperand())) {
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if (isLegalMaskedLoad(LI->getType(), LI->getPointerOperand())) {
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MaskedOp.insert(LI);
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continue;
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}
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return false;
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}
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}
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// We don't predicate stores at the moment.
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if (it->mayWriteToMemory()) {
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StoreInst *SI = dyn_cast<StoreInst>(it);
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// We only support predication of stores in basic blocks with one
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// predecessor.
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if (!SI)
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return false;
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bool isSafePtr = (SafePtrs.count(SI->getPointerOperand()) != 0);
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bool isSinglePredecessor = SI->getParent()->getSinglePredecessor();
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if (++NumPredStores > NumberOfStoresToPredicate || !isSafePtr ||
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!isSinglePredecessor) {
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// Build a masked store if it is legal for the target, otherwise scalarize
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// the block.
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bool isLegalMaskedOp =
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isLegalMaskedStore(SI->getValueOperand()->getType(),
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SI->getPointerOperand());
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if (isLegalMaskedOp) {
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--NumPredStores;
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MaskedOp.insert(SI);
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continue;
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}
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return false;
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}
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}
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if (it->mayThrow())
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return false;
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// The instructions below can trap.
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switch (it->getOpcode()) {
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420
test/Transforms/LoopVectorize/X86/masked_load_store.ll
Normal file
420
test/Transforms/LoopVectorize/X86/masked_load_store.ll
Normal file
@ -0,0 +1,420 @@
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; RUN: opt < %s -O3 -mcpu=corei7-avx -S | FileCheck %s -check-prefix=AVX1
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; RUN: opt < %s -O3 -mcpu=core-avx2 -S | FileCheck %s -check-prefix=AVX2
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; RUN: opt < %s -O3 -mcpu=knl -S | FileCheck %s -check-prefix=AVX512
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;AVX1-NOT: llvm.masked
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-pc_linux"
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; The source code:
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;
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;void foo1(int *A, int *B, int *trigger) {
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;
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; for (int i=0; i<10000; i++) {
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; if (trigger[i] < 100) {
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; A[i] = B[i] + trigger[i];
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; }
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; }
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;}
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;AVX2-LABEL: @foo1
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;AVX2: icmp slt <8 x i32> %wide.load, <i32 100, i32 100, i32 100
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;AVX2: call <8 x i32> @llvm.masked.load.v8i32
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;AVX2: add nsw <8 x i32>
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;AVX2: call void @llvm.masked.store.v8i32
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;AVX2: ret void
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;AVX512-LABEL: @foo1
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;AVX512: icmp slt <16 x i32> %wide.load, <i32 100, i32 100, i32 100
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;AVX512: call <16 x i32> @llvm.masked.load.v16i32
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;AVX512: add nsw <16 x i32>
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;AVX512: call void @llvm.masked.store.v16i32
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;AVX512: ret void
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; Function Attrs: nounwind uwtable
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define void @foo1(i32* %A, i32* %B, i32* %trigger) {
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entry:
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%A.addr = alloca i32*, align 8
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%B.addr = alloca i32*, align 8
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%trigger.addr = alloca i32*, align 8
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%i = alloca i32, align 4
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store i32* %A, i32** %A.addr, align 8
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store i32* %B, i32** %B.addr, align 8
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store i32* %trigger, i32** %trigger.addr, align 8
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store i32 0, i32* %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%0 = load i32* %i, align 4
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%cmp = icmp slt i32 %0, 10000
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%1 = load i32* %i, align 4
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%idxprom = sext i32 %1 to i64
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%2 = load i32** %trigger.addr, align 8
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%arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
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%3 = load i32* %arrayidx, align 4
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%cmp1 = icmp slt i32 %3, 100
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %for.body
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%4 = load i32* %i, align 4
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%idxprom2 = sext i32 %4 to i64
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%5 = load i32** %B.addr, align 8
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%arrayidx3 = getelementptr inbounds i32* %5, i64 %idxprom2
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%6 = load i32* %arrayidx3, align 4
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%7 = load i32* %i, align 4
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%idxprom4 = sext i32 %7 to i64
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%8 = load i32** %trigger.addr, align 8
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%arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
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%9 = load i32* %arrayidx5, align 4
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%add = add nsw i32 %6, %9
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%10 = load i32* %i, align 4
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%idxprom6 = sext i32 %10 to i64
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%11 = load i32** %A.addr, align 8
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%arrayidx7 = getelementptr inbounds i32* %11, i64 %idxprom6
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store i32 %add, i32* %arrayidx7, align 4
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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br label %for.inc
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for.inc: ; preds = %if.end
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%12 = load i32* %i, align 4
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%inc = add nsw i32 %12, 1
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store i32 %inc, i32* %i, align 4
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br label %for.cond
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for.end: ; preds = %for.cond
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ret void
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}
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; The source code:
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;
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;void foo2(float *A, float *B, int *trigger) {
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;
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; for (int i=0; i<10000; i++) {
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; if (trigger[i] < 100) {
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; A[i] = B[i] + trigger[i];
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; }
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; }
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;}
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;AVX2-LABEL: @foo2
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;AVX2: icmp slt <8 x i32> %wide.load, <i32 100, i32 100, i32 100
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;AVX2: call <8 x float> @llvm.masked.load.v8f32
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;AVX2: fadd <8 x float>
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;AVX2: call void @llvm.masked.store.v8f32
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;AVX2: ret void
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;AVX512-LABEL: @foo2
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;AVX512: icmp slt <16 x i32> %wide.load, <i32 100, i32 100, i32 100
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;AVX512: call <16 x float> @llvm.masked.load.v16f32
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;AVX512: fadd <16 x float>
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;AVX512: call void @llvm.masked.store.v16f32
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;AVX512: ret void
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; Function Attrs: nounwind uwtable
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define void @foo2(float* %A, float* %B, i32* %trigger) {
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entry:
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%A.addr = alloca float*, align 8
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%B.addr = alloca float*, align 8
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%trigger.addr = alloca i32*, align 8
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%i = alloca i32, align 4
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store float* %A, float** %A.addr, align 8
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store float* %B, float** %B.addr, align 8
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store i32* %trigger, i32** %trigger.addr, align 8
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store i32 0, i32* %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%0 = load i32* %i, align 4
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%cmp = icmp slt i32 %0, 10000
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%1 = load i32* %i, align 4
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%idxprom = sext i32 %1 to i64
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%2 = load i32** %trigger.addr, align 8
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%arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
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%3 = load i32* %arrayidx, align 4
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%cmp1 = icmp slt i32 %3, 100
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %for.body
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%4 = load i32* %i, align 4
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%idxprom2 = sext i32 %4 to i64
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%5 = load float** %B.addr, align 8
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%arrayidx3 = getelementptr inbounds float* %5, i64 %idxprom2
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%6 = load float* %arrayidx3, align 4
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%7 = load i32* %i, align 4
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%idxprom4 = sext i32 %7 to i64
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%8 = load i32** %trigger.addr, align 8
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%arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
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%9 = load i32* %arrayidx5, align 4
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%conv = sitofp i32 %9 to float
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%add = fadd float %6, %conv
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%10 = load i32* %i, align 4
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%idxprom6 = sext i32 %10 to i64
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%11 = load float** %A.addr, align 8
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%arrayidx7 = getelementptr inbounds float* %11, i64 %idxprom6
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store float %add, float* %arrayidx7, align 4
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br label %if.end
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if.end: ; preds = %if.then, %for.body
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br label %for.inc
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for.inc: ; preds = %if.end
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%12 = load i32* %i, align 4
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%inc = add nsw i32 %12, 1
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store i32 %inc, i32* %i, align 4
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br label %for.cond
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for.end: ; preds = %for.cond
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ret void
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}
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; The source code:
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;
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;void foo3(double *A, double *B, int *trigger) {
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;
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; for (int i=0; i<10000; i++) {
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; if (trigger[i] < 100) {
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; A[i] = B[i] + trigger[i];
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; }
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; }
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;}
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;AVX2-LABEL: @foo3
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;AVX2: icmp slt <4 x i32> %wide.load, <i32 100, i32 100,
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;AVX2: call <4 x double> @llvm.masked.load.v4f64
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;AVX2: sitofp <4 x i32> %wide.load to <4 x double>
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;AVX2: fadd <4 x double>
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;AVX2: call void @llvm.masked.store.v4f64
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;AVX2: ret void
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;AVX512-LABEL: @foo3
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||||
;AVX512: icmp slt <8 x i32> %wide.load, <i32 100, i32 100,
|
||||
;AVX512: call <8 x double> @llvm.masked.load.v8f64
|
||||
;AVX512: sitofp <8 x i32> %wide.load to <8 x double>
|
||||
;AVX512: fadd <8 x double>
|
||||
;AVX512: call void @llvm.masked.store.v8f64
|
||||
;AVX512: ret void
|
||||
|
||||
|
||||
; Function Attrs: nounwind uwtable
|
||||
define void @foo3(double* %A, double* %B, i32* %trigger) #0 {
|
||||
entry:
|
||||
%A.addr = alloca double*, align 8
|
||||
%B.addr = alloca double*, align 8
|
||||
%trigger.addr = alloca i32*, align 8
|
||||
%i = alloca i32, align 4
|
||||
store double* %A, double** %A.addr, align 8
|
||||
store double* %B, double** %B.addr, align 8
|
||||
store i32* %trigger, i32** %trigger.addr, align 8
|
||||
store i32 0, i32* %i, align 4
|
||||
br label %for.cond
|
||||
|
||||
for.cond: ; preds = %for.inc, %entry
|
||||
%0 = load i32* %i, align 4
|
||||
%cmp = icmp slt i32 %0, 10000
|
||||
br i1 %cmp, label %for.body, label %for.end
|
||||
|
||||
for.body: ; preds = %for.cond
|
||||
%1 = load i32* %i, align 4
|
||||
%idxprom = sext i32 %1 to i64
|
||||
%2 = load i32** %trigger.addr, align 8
|
||||
%arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
|
||||
%3 = load i32* %arrayidx, align 4
|
||||
%cmp1 = icmp slt i32 %3, 100
|
||||
br i1 %cmp1, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %for.body
|
||||
%4 = load i32* %i, align 4
|
||||
%idxprom2 = sext i32 %4 to i64
|
||||
%5 = load double** %B.addr, align 8
|
||||
%arrayidx3 = getelementptr inbounds double* %5, i64 %idxprom2
|
||||
%6 = load double* %arrayidx3, align 8
|
||||
%7 = load i32* %i, align 4
|
||||
%idxprom4 = sext i32 %7 to i64
|
||||
%8 = load i32** %trigger.addr, align 8
|
||||
%arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
|
||||
%9 = load i32* %arrayidx5, align 4
|
||||
%conv = sitofp i32 %9 to double
|
||||
%add = fadd double %6, %conv
|
||||
%10 = load i32* %i, align 4
|
||||
%idxprom6 = sext i32 %10 to i64
|
||||
%11 = load double** %A.addr, align 8
|
||||
%arrayidx7 = getelementptr inbounds double* %11, i64 %idxprom6
|
||||
store double %add, double* %arrayidx7, align 8
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %for.body
|
||||
br label %for.inc
|
||||
|
||||
for.inc: ; preds = %if.end
|
||||
%12 = load i32* %i, align 4
|
||||
%inc = add nsw i32 %12, 1
|
||||
store i32 %inc, i32* %i, align 4
|
||||
br label %for.cond
|
||||
|
||||
for.end: ; preds = %for.cond
|
||||
ret void
|
||||
}
|
||||
|
||||
; The source code:
|
||||
;
|
||||
;void foo4(double *A, double *B, int *trigger) {
|
||||
;
|
||||
; for (int i=0; i<10000; i++) {
|
||||
; if (trigger[i] < 100) {
|
||||
; A[i] = B[i*2] + trigger[i]; << non-cosecutive access
|
||||
; }
|
||||
; }
|
||||
;}
|
||||
|
||||
;AVX2-LABEL: @foo4
|
||||
;AVX2-NOT: llvm.masked
|
||||
;AVX2: ret void
|
||||
|
||||
;AVX512-LABEL: @foo4
|
||||
;AVX512-NOT: llvm.masked
|
||||
;AVX512: ret void
|
||||
|
||||
; Function Attrs: nounwind uwtable
|
||||
define void @foo4(double* %A, double* %B, i32* %trigger) {
|
||||
entry:
|
||||
%A.addr = alloca double*, align 8
|
||||
%B.addr = alloca double*, align 8
|
||||
%trigger.addr = alloca i32*, align 8
|
||||
%i = alloca i32, align 4
|
||||
store double* %A, double** %A.addr, align 8
|
||||
store double* %B, double** %B.addr, align 8
|
||||
store i32* %trigger, i32** %trigger.addr, align 8
|
||||
store i32 0, i32* %i, align 4
|
||||
br label %for.cond
|
||||
|
||||
for.cond: ; preds = %for.inc, %entry
|
||||
%0 = load i32* %i, align 4
|
||||
%cmp = icmp slt i32 %0, 10000
|
||||
br i1 %cmp, label %for.body, label %for.end
|
||||
|
||||
for.body: ; preds = %for.cond
|
||||
%1 = load i32* %i, align 4
|
||||
%idxprom = sext i32 %1 to i64
|
||||
%2 = load i32** %trigger.addr, align 8
|
||||
%arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
|
||||
%3 = load i32* %arrayidx, align 4
|
||||
%cmp1 = icmp slt i32 %3, 100
|
||||
br i1 %cmp1, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %for.body
|
||||
%4 = load i32* %i, align 4
|
||||
%mul = mul nsw i32 %4, 2
|
||||
%idxprom2 = sext i32 %mul to i64
|
||||
%5 = load double** %B.addr, align 8
|
||||
%arrayidx3 = getelementptr inbounds double* %5, i64 %idxprom2
|
||||
%6 = load double* %arrayidx3, align 8
|
||||
%7 = load i32* %i, align 4
|
||||
%idxprom4 = sext i32 %7 to i64
|
||||
%8 = load i32** %trigger.addr, align 8
|
||||
%arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
|
||||
%9 = load i32* %arrayidx5, align 4
|
||||
%conv = sitofp i32 %9 to double
|
||||
%add = fadd double %6, %conv
|
||||
%10 = load i32* %i, align 4
|
||||
%idxprom6 = sext i32 %10 to i64
|
||||
%11 = load double** %A.addr, align 8
|
||||
%arrayidx7 = getelementptr inbounds double* %11, i64 %idxprom6
|
||||
store double %add, double* %arrayidx7, align 8
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %for.body
|
||||
br label %for.inc
|
||||
|
||||
for.inc: ; preds = %if.end
|
||||
%12 = load i32* %i, align 4
|
||||
%inc = add nsw i32 %12, 1
|
||||
store i32 %inc, i32* %i, align 4
|
||||
br label %for.cond
|
||||
|
||||
for.end: ; preds = %for.cond
|
||||
ret void
|
||||
}
|
||||
|
||||
@a = common global [1 x i32*] zeroinitializer, align 8
|
||||
@c = common global i32* null, align 8
|
||||
|
||||
; The loop here should not be vectorized due to trapping
|
||||
; constant expression
|
||||
;AVX2-LABEL: @foo5
|
||||
;AVX2-NOT: llvm.masked
|
||||
;AVX2: store i32 sdiv
|
||||
;AVX2: ret void
|
||||
|
||||
;AVX512-LABEL: @foo5
|
||||
;AVX512-NOT: llvm.masked
|
||||
;AVX512: store i32 sdiv
|
||||
;AVX512: ret void
|
||||
|
||||
; Function Attrs: nounwind uwtable
|
||||
define void @foo5(i32* %A, i32* %B, i32* %trigger) {
|
||||
entry:
|
||||
%A.addr = alloca i32*, align 8
|
||||
%B.addr = alloca i32*, align 8
|
||||
%trigger.addr = alloca i32*, align 8
|
||||
%i = alloca i32, align 4
|
||||
store i32* %A, i32** %A.addr, align 8
|
||||
store i32* %B, i32** %B.addr, align 8
|
||||
store i32* %trigger, i32** %trigger.addr, align 8
|
||||
store i32 0, i32* %i, align 4
|
||||
br label %for.cond
|
||||
|
||||
for.cond: ; preds = %for.inc, %entry
|
||||
%0 = load i32* %i, align 4
|
||||
%cmp = icmp slt i32 %0, 10000
|
||||
br i1 %cmp, label %for.body, label %for.end
|
||||
|
||||
for.body: ; preds = %for.cond
|
||||
%1 = load i32* %i, align 4
|
||||
%idxprom = sext i32 %1 to i64
|
||||
%2 = load i32** %trigger.addr, align 8
|
||||
%arrayidx = getelementptr inbounds i32* %2, i64 %idxprom
|
||||
%3 = load i32* %arrayidx, align 4
|
||||
%cmp1 = icmp slt i32 %3, 100
|
||||
br i1 %cmp1, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %for.body
|
||||
%4 = load i32* %i, align 4
|
||||
%idxprom2 = sext i32 %4 to i64
|
||||
%5 = load i32** %B.addr, align 8
|
||||
%arrayidx3 = getelementptr inbounds i32* %5, i64 %idxprom2
|
||||
%6 = load i32* %arrayidx3, align 4
|
||||
%7 = load i32* %i, align 4
|
||||
%idxprom4 = sext i32 %7 to i64
|
||||
%8 = load i32** %trigger.addr, align 8
|
||||
%arrayidx5 = getelementptr inbounds i32* %8, i64 %idxprom4
|
||||
%9 = load i32* %arrayidx5, align 4
|
||||
%add = add nsw i32 %6, %9
|
||||
%10 = load i32* %i, align 4
|
||||
%idxprom6 = sext i32 %10 to i64
|
||||
%11 = load i32** %A.addr, align 8
|
||||
%arrayidx7 = getelementptr inbounds i32* %11, i64 %idxprom6
|
||||
store i32 sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*]* @a, i64 0, i64 1), i32** @c) to i32)), i32* %arrayidx7, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %for.body
|
||||
br label %for.inc
|
||||
|
||||
for.inc: ; preds = %if.end
|
||||
%12 = load i32* %i, align 4
|
||||
%inc = add nsw i32 %12, 1
|
||||
store i32 %inc, i32* %i, align 4
|
||||
br label %for.cond
|
||||
|
||||
for.end: ; preds = %for.cond
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user