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The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td

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entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894
This commit is contained in:
Johnny Chen 2010-08-12 01:40:54 +00:00
parent 4f45de1b1e
commit fef1367b50
3 changed files with 11 additions and 0 deletions
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7
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -26,6 +26,8 @@
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
//#define DEBUG(X) do { X; } while (0)
/// ARMGenDecoderTables.inc - ARMDecoderTables.inc is tblgen'ed from /// ARMGenDecoderTables.inc - ARMDecoderTables.inc is tblgen'ed from
/// ARMDecoderEmitter.cpp TableGen backend. It contains: /// ARMDecoderEmitter.cpp TableGen backend. It contains:
/// ///
@ -87,6 +89,11 @@ static unsigned decodeARMInstruction(uint32_t &insn) {
return ARM::BFI; return ARM::BFI;
} }
// Ditto for STRBT, which is a super-instruction for A8.6.199 Encoding A1 & A2.
// As a result, the decoder fails to deocode USAT properly.
if (slice(insn, 27, 21) == 0x37 && slice(insn, 5, 4) == 1)
return ARM::USAT;
// Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8. // Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8.
// As a result, the decoder fails to decode UMULL properly. // As a result, the decoder fails to decode UMULL properly.
if (slice(insn, 27, 21) == 0x04 && slice(insn, 7, 4) == 9) { if (slice(insn, 27, 21) == 0x04 && slice(insn, 7, 4) == 9) {

2
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -20,6 +20,8 @@
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
//#define DEBUG(X) do { X; } while (0)
/// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
/// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s /// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s
/// describing the operand info for each ARMInsts[i]. /// describing the operand info for each ARMInsts[i].

2
test/MC/Disassembler/arm-tests.txt
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@ -97,3 +97,5 @@
# CHECK: ubfx r0, r0, #16, #1 # CHECK: ubfx r0, r0, #16, #1
0x50 0x08 0xe0 0xe7 0x50 0x08 0xe0 0xe7
# CHECK: usat r8, #0, r10, asr #32
0x5a 0x80 0xe0 0xe6