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fix typos in comments; NFC

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llvm-svn: 308127
This commit is contained in:
Hiroshi Inoue 2017-07-16 08:11:56 +00:00
parent a45f824308
commit fefa37bba8
5 changed files with 5 additions and 5 deletions
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2
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -885,7 +885,7 @@ CCAssignFn *AMDGPUCallLowering::CCAssignFnForReturn(CallingConv::ID CC,
/// When the SelectionDAGBuilder computes the Ins, it takes care of splitting /// When the SelectionDAGBuilder computes the Ins, it takes care of splitting
/// input values across multiple registers. Each item in the Ins array /// input values across multiple registers. Each item in the Ins array
/// represents a single value that will be stored in regsters. Ins[x].VT is /// represents a single value that will be stored in registers. Ins[x].VT is
/// the value type of the value that will be stored in the register, so /// the value type of the value that will be stored in the register, so
/// whatever SDNode we lower the argument to needs to be this type. /// whatever SDNode we lower the argument to needs to be this type.
/// ///

2
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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@ -1208,7 +1208,7 @@ bool AMDGPUOperand::isInlinableImm(MVT type) const {
} }
bool AMDGPUOperand::isLiteralImm(MVT type) const { bool AMDGPUOperand::isLiteralImm(MVT type) const {
// Check that this imediate can be added as literal // Check that this immediate can be added as literal
if (!isImmTy(ImmTyNone)) { if (!isImmTy(ImmTyNone)) {
return false; return false;
} }

2
lib/Target/X86/X86FixupBWInsts.cpp
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@ -22,7 +22,7 @@
/// instructions and register-to-register moves. It would /// instructions and register-to-register moves. It would
/// seem like cmov(s) would also be affected, but because of the way cmov is /// seem like cmov(s) would also be affected, but because of the way cmov is
/// really implemented by most machines as reading both the destination and /// really implemented by most machines as reading both the destination and
/// and source regsters, and then "merging" the two based on a condition, /// and source registers, and then "merging" the two based on a condition,
/// it really already should be considered as having a true dependence on the /// it really already should be considered as having a true dependence on the
/// destination register as well. /// destination register as well.
/// ///

2
test/CodeGen/AMDGPU/parallelandifcollapse.ll
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@ -8,7 +8,7 @@
; CHECK-NEXT: OR_INT ; CHECK-NEXT: OR_INT
; FIXME: For some reason having the allocas here allowed the flatten cfg pass ; FIXME: For some reason having the allocas here allowed the flatten cfg pass
; to do its transfomation, however now that we are using local memory for ; to do its transformation, however now that we are using local memory for
; allocas, the transformation isn't happening. ; allocas, the transformation isn't happening.
define amdgpu_kernel void @_Z9chk1D_512v() #0 { define amdgpu_kernel void @_Z9chk1D_512v() #0 {

2
test/CodeGen/AMDGPU/parallelorifcollapse.ll
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@ -5,7 +5,7 @@
; then merge if-regions with the same bodies. ; then merge if-regions with the same bodies.
; FIXME: For some reason having the allocas here allowed the flatten cfg pass ; FIXME: For some reason having the allocas here allowed the flatten cfg pass
; to do its transfomation, however now that we are using local memory for ; to do its transformation, however now that we are using local memory for
; allocas, the transformation isn't happening. ; allocas, the transformation isn't happening.
; XFAIL: * ; XFAIL: *
; ;