mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-24 04:25:22 +00:00
Fix a dagcombine to not generate loads of non-round integer types,
as its comment says, even in the case where it will be generating extending loads. This fixes PR3216. llvm-svn: 62557
This commit is contained in:
parent
6a88f8849b
commit
ff4c4ab39f
@ -3343,7 +3343,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
|
||||
|
||||
// Do not generate loads of non-round integer types since these can
|
||||
// be expensive (and would be wrong if the type is not byte sized).
|
||||
if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() &&
|
||||
if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
|
||||
cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
|
||||
// Do not change the width of a volatile load.
|
||||
!cast<LoadSDNode>(N0)->isVolatile()) {
|
||||
|
14
test/CodeGen/X86/pr3216.ll
Normal file
14
test/CodeGen/X86/pr3216.ll
Normal file
@ -0,0 +1,14 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 | grep {sar. \$5}
|
||||
|
||||
@foo = global i8 127
|
||||
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
%tmp = load i8* @foo
|
||||
%bf.lo = lshr i8 %tmp, 5
|
||||
%bf.lo.cleared = and i8 %bf.lo, 7
|
||||
%0 = shl i8 %bf.lo.cleared, 5
|
||||
%bf.val.sext = ashr i8 %0, 5
|
||||
%conv = sext i8 %bf.val.sext to i32
|
||||
ret i32 %conv
|
||||
}
|
Loading…
Reference in New Issue
Block a user