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Fix a dagcombine to not generate loads of non-round integer types,
as its comment says, even in the case where it will be generating extending loads. This fixes PR3216. llvm-svn: 62557
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@ -3343,7 +3343,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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// Do not generate loads of non-round integer types since these can
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// Do not generate loads of non-round integer types since these can
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// be expensive (and would be wrong if the type is not byte sized).
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// be expensive (and would be wrong if the type is not byte sized).
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if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() &&
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if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
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cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
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cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
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// Do not change the width of a volatile load.
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// Do not change the width of a volatile load.
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!cast<LoadSDNode>(N0)->isVolatile()) {
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!cast<LoadSDNode>(N0)->isVolatile()) {
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14
test/CodeGen/X86/pr3216.ll
Normal file
14
test/CodeGen/X86/pr3216.ll
Normal file
@ -0,0 +1,14 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep {sar. \$5}
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@foo = global i8 127
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define i32 @main() nounwind {
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entry:
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%tmp = load i8* @foo
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%bf.lo = lshr i8 %tmp, 5
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%bf.lo.cleared = and i8 %bf.lo, 7
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%0 = shl i8 %bf.lo.cleared, 5
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%bf.val.sext = ashr i8 %0, 5
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%conv = sext i8 %bf.val.sext to i32
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ret i32 %conv
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}
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