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Provide expansion for ct* intrinsics
llvm-svn: 76311
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@ -106,6 +106,13 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTPOP, MVT::i64, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i64, Expand);
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setOperationAction(ISD::CTLZ, MVT::i32, Promote);
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setOperationAction(ISD::CTLZ, MVT::i64, Legal);
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// FIXME: Can we lower these 2 efficiently?
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setOperationAction(ISD::SETCC, MVT::i32, Expand);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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@ -941,6 +941,15 @@ def UCMPZX64rm32 : RXYI<0xE331,
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} // Defs = [PSW]
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//===----------------------------------------------------------------------===//
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// Other crazy stuff
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let Defs = [PSW] in {
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def FLOGR64 : RREI<0xB983,
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(outs GR128:$dst), (ins GR64:$src),
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"flogr\t{$dst, $src}",
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[]>;
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} // Defs = [PSW]
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns.
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//===----------------------------------------------------------------------===//
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@ -1003,3 +1012,6 @@ def : Pat<(mulhu GR64:$src1, GR64:$src2),
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GR64:$src1, subreg_odd),
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GR64:$src2),
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subreg_even)>;
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def : Pat<(ctlz GR64:$src),
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(EXTRACT_SUBREG (FLOGR64 GR64:$src), subreg_even)>;
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