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Add stub for RAGreedy::trySplit.

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llvm-svn: 121736
This commit is contained in:
Jakob Stoklund Olesen 2010-12-14 00:37:44 +00:00
parent c84f8c23b3
commit ffefd5bd4e
1 changed files with 16 additions and 0 deletions
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16
lib/CodeGen/RegAllocGreedy.cpp
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@ -83,6 +83,9 @@ private:
bool checkUncachedInterference(LiveInterval &, unsigned);
bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
unsigned trySplit(LiveInterval&, AllocationOrder&,
SmallVectorImpl<LiveInterval*>&);
};
} // end anonymous namespace
@ -222,6 +225,15 @@ bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) {
return reassignVReg(*Q.interferingVRegs()[0], PhysReg);
}
/// trySplit - Try to split VirtReg or one of its interferences, making it
/// assignable.
/// @return Physreg when VirtReg may be assigned and/or new SplitVRegs.
unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
SmallVectorImpl<LiveInterval*>&SplitVRegs) {
NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
return 0;
}
unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<LiveInterval*> &SplitVRegs) {
// Populate a list of physical register spill candidates.
@ -266,6 +278,10 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
ReassignCands.end());
unsigned PhysReg = trySplit(VirtReg, Order, SplitVRegs);
if (PhysReg || !SplitVRegs.empty())
return PhysReg;
// Try to spill another interfering reg with less spill weight.
NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
//