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Commit Graph

Author	SHA1	Message	Date
Dan Gohman	5f6f8101d5	Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897	2009-06-04 22:49:04 +00:00
Evan Cheng	4014a9a5b8	ADDS{D\|S}rr_Int and MULS{D\|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified. llvm-svn: 65499	2009-02-26 03:12:02 +00:00

Author

SHA1

Message

Date

Dan Gohman

5f6f8101d5

Split the Add, Sub, and Mul instruction opcodes into separate

integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897

2009-06-04 22:49:04 +00:00

Evan Cheng

4014a9a5b8

ADDS{D|S}rr_Int and MULS{D|S}rr_Int are not commutable. The users of these intrinsics expect the high bits will not be modified.

llvm-svn: 65499

2009-02-26 03:12:02 +00:00

2 Commits