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82 Commits

Author SHA1 Message Date
Richard Osborne
962b1ca071 Associate a MemOperand with LDWCP nodes introduced during ISel. 
This information is required if we want LDWCP to be hoisted out of loops.

llvm-svn: 139495
 2011-09-12 14:43:23 +00:00
Duncan Sands
6939ae53ac Split the init.trampoline intrinsic, which currently combines GCC's 
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140
 2011-09-06 13:37:06 +00:00
Richard Osborne
6b6b0b535d Add Uses=[SP] to call instructions. This fixes a miscompilation with a 
variable sized alloca.

llvm-svn: 138433
 2011-08-24 13:32:43 +00:00
Richard Osborne
415c5ff412 Add intrinsics for SETEV, GETED, GETET. 
llvm-svn: 137938
 2011-08-18 13:00:48 +00:00
Richard Osborne
2cd07cf351 Fix crash with varargs function with no named parameters. 
llvm-svn: 136623
 2011-08-01 16:45:59 +00:00
Richard Osborne
b469141419 Add intrinsics for the zext / sext instructions. 
llvm-svn: 135476
 2011-07-19 13:28:50 +00:00
Richard Osborne
50303e0d38 Add intrinsics for the testct, testwct instructions. 
llvm-svn: 135475
 2011-07-19 13:00:40 +00:00
Richard Osborne
409c0d7768 Add intrinsics for the peek and endin instructions. 
llvm-svn: 135474
 2011-07-19 12:50:25 +00:00
Chris Lattner
0899957b99 make the asmparser reject function and type redefinitions. 'Merging' hasn't been 
needed since llvm-gcc 3.4 days.

llvm-svn: 133248
 2011-06-17 07:06:44 +00:00
Richard Osborne
4293c93896 Add XCore intrinsic for crc8. 
llvm-svn: 132340
 2011-05-31 16:24:49 +00:00
Richard Osborne
34a4652dcd Add XCore intrinsic for crc32. 
llvm-svn: 132336
 2011-05-31 14:47:36 +00:00
Richard Osborne
d84d3d1068 Convert test to FileCheck. 
llvm-svn: 132335
 2011-05-31 14:00:05 +00:00
Jakob Stoklund Olesen
20af0b593b Fix register-dependent XCore tests 
llvm-svn: 130816
 2011-05-04 01:01:41 +00:00
Jakob Stoklund Olesen
36c7c9d42d Fix Mips, Sparc, and XCore tests that were dependent on register allocation. 
Add an extra run with -regalloc=basic to keep them honest.

llvm-svn: 128654
 2011-03-31 18:42:43 +00:00
Richard Osborne
5b9df0d075 Add XCore intrinsics for initializing / starting / synchronizing threads. 
llvm-svn: 128633
 2011-03-31 15:13:13 +00:00
Richard Osborne
6bad79b514 Add XCore intrinsic for setpsc. 
llvm-svn: 127821
 2011-03-17 18:42:05 +00:00
Richard Osborne
8b90369d96 Add XCore intrinsics for setclk, setrdy. 
llvm-svn: 127761
 2011-03-16 21:56:00 +00:00
Richard Osborne
318e25c620 Add checkevent intrinsic to check if any resources owned by the current thread 
can event.

llvm-svn: 127741
 2011-03-16 18:34:00 +00:00
Richard Osborne
af1b66c427 On the XCore the scavenging slot should be closest to the SP. 
llvm-svn: 127680
 2011-03-15 15:10:11 +00:00
Richard Osborne
70204c1c29 Add XCore intrinsics for getps, setps, setsr and clrsr. 
llvm-svn: 127678
 2011-03-15 13:45:47 +00:00
Benjamin Kramer
8313cf1cf4 Fix mistyped CHECK lines. 
llvm-svn: 127366
 2011-03-09 22:07:31 +00:00
Joerg Sonnenberger
5f2f5fa638 Be nice to Xcore and the XMOS assembler and avoid quoting section names 
that contain only letters, digits and the characters "_" and ".".

llvm-svn: 127028
 2011-03-04 20:03:14 +00:00
Joerg Sonnenberger
bb93506f95 Bug#9033: For the ELF assembler output, always quote the section name. 
llvm-svn: 126963
 2011-03-03 22:31:08 +00:00
Richard Osborne
a8df984a31 Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00
Richard Osborne
d9564589f6 Add XCore intrinsic for clre instruction. 
llvm-svn: 126322
 2011-02-23 18:52:05 +00:00
Richard Osborne
4a55817288 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320
 2011-02-23 18:35:59 +00:00
Richard Osborne
aaac1b01fd Add XCore intrinsic for the setv instruction. 
llvm-svn: 126315
 2011-02-23 16:46:37 +00:00
Richard Osborne
aa39bf94b4 Add XCore intrinsic for settw instruction. 
llvm-svn: 126313
 2011-02-23 14:45:03 +00:00
Richard Osborne
bd0e21b5ca Add XCore intrinsics for various instructions on ports. 
llvm-svn: 126132
 2011-02-21 18:23:30 +00:00
Richard Osborne
112cff2533 Add intrinsic for setc instruction on the XCore. 
llvm-svn: 125186
 2011-02-09 13:22:12 +00:00
Richard Osborne
5c655f451e Add XCore intrinsics for resource instructions. 
llvm-svn: 124794
 2011-02-03 13:14:25 +00:00
Richard Osborne
5ee859cb22 Add support for trampolines on the XCore. 
llvm-svn: 124722
 2011-02-02 14:57:41 +00:00
Richard Osborne
11cdda2346 Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions. 
llvm-svn: 124587
 2011-01-31 17:41:44 +00:00
Rafael Espindola
9afb7af08a Update tests. 
llvm-svn: 123591
 2011-01-16 18:02:57 +00:00
Devang Patel
6fe7fe8dd4 If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0. 
llvm-svn: 121059
 2010-12-06 22:39:26 +00:00
Evan Cheng
1ce02d180e Enable machine sinking critical edge splitting. e.g. 
define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886

llvm-svn: 114372
 2010-09-20 22:52:00 +00:00
Dan Gohman
5736cd1e47 Start function numbering at 0. 
llvm-svn: 101638
 2010-04-17 16:29:15 +00:00
Dale Johannesen
4cdb545401 Split big test into multiple directories to cater to 
those who don't build all targets.

llvm-svn: 100688
 2010-04-07 20:43:35 +00:00
Chris Lattner
2bdb0765f8 fix AsmPrinter::GetBlockAddressSymbol to always return a unique 
label instead of trying to form one based on the BB name (which
causes collisions if the name is empty).  This fixes PR6608

llvm-svn: 98495
 2010-03-14 17:53:23 +00:00
Richard Osborne
0dcde97cbc Add dag combine to simplify lmul(x, 0, a, b) 
llvm-svn: 98258
 2010-03-11 16:26:35 +00:00
Richard Osborne
41c5f84f1d Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit 
expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.

llvm-svn: 98168
 2010-03-10 18:12:27 +00:00
Richard Osborne
d400202a43 Fold add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if the intermediate 
results are unused elsewhere.

llvm-svn: 98157
 2010-03-10 16:19:31 +00:00
Richard Osborne
c19c2bd177 Prefer LMUL to MACCU as LMUL has no tied operands. 
llvm-svn: 98153
 2010-03-10 13:27:10 +00:00
Richard Osborne
43210638f1 Custom lower (S|U)MUL_LOHI -> MACC(S|U) 
llvm-svn: 98152
 2010-03-10 13:20:07 +00:00
Richard Osborne
c88a8e8d66 Lower add (mul a, b), c into MACCU / MACCS nodes which translate 
directly to the maccu / maccs instructions. We handle this in
ExpandADDSUB since after type legalisation it is messy to
recognise these operations.

llvm-svn: 98150
 2010-03-10 11:41:08 +00:00
Richard Osborne
6c55bfe516 Convert test to FileCheck. 
llvm-svn: 98148
 2010-03-10 11:24:03 +00:00
Richard Osborne
4077517135 In cases where the carry / borrow unused converted ladd / lsub 
to an add or a sub.

llvm-svn: 98059
 2010-03-09 16:34:25 +00:00
Richard Osborne
173efed224 Add DAG combine for ladd / lsub. 
llvm-svn: 98057
 2010-03-09 16:07:47 +00:00
Richard Osborne
fe30a8a2c1 Fix XCoreTargetLowering::isLegalAddressingMode() to handle VoidTy. 
Previously LoopStrengthReduce would sometimes be unable to find
a legal formula, causing an assertion failure.

llvm-svn: 97226
 2010-02-26 16:44:51 +00:00
Richard Osborne
7387249531 Lower BR_JT on the XCore to a jump into a series of jump instructions. 
llvm-svn: 96942
 2010-02-23 13:25:07 +00:00