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17912 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
0ac5f2eaf8 Blackfin always uses a reserved call frame. 
Materializing the stack pointer update before a call requires a scratch
register that may not be available.

llvm-svn: 132601
 2011-06-03 22:45:18 +00:00
Eric Christopher
e831655dd9 Make the Uv constraint a memory operand. This doesn't solve the 
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561
 2011-06-03 17:24:37 +00:00
Roman Divacky
3624922127 Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant. 
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.

llvm-svn: 132552
 2011-06-03 15:47:49 +00:00
Eli Friedman
eae10d6163 Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. 
rdar://9431157

llvm-svn: 132522
 2011-06-03 01:13:19 +00:00
Eric Christopher
d68494ffdd Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939

llvm-svn: 132510
 2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen
409986a648 Flag unallocatable register classes instead of giving them empty 
allocation orders.

llvm-svn: 132509
 2011-06-02 23:07:24 +00:00
Jakob Stoklund Olesen
4f76a2bdc8 Make it possible to have unallocatable register classes. 
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508
 2011-06-02 23:07:20 +00:00
Tanya Lattner
aa1f6df650 Fix encoding for VEXTdf. 
llvm-svn: 132486
 2011-06-02 21:25:24 +00:00
Rafael Espindola
1299f014d4 Revert 132424 to fix PR10068. 
llvm-svn: 132479
 2011-06-02 19:57:47 +00:00
Stuart Hastings
8447f18f85 Omit unnecessary stack copy when x87 input is a load. 
rdar://problem/6373334

llvm-svn: 132458
 2011-06-02 15:57:11 +00:00
Jakob Stoklund Olesen
25716baae0 Use TRI::has{Sub,Super}ClassEq() where possible. 
No functional change.

llvm-svn: 132455
 2011-06-02 05:43:46 +00:00
Rafael Espindola
ee123951a2 Don't hardcode the %reg format in the streamer. 
llvm-svn: 132451
 2011-06-02 02:34:55 +00:00
Akira Hatanaka
1f91013bcb Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic. 
llvm-svn: 132448
 2011-06-02 01:03:14 +00:00
Akira Hatanaka
69ae562f33 Custom-lower FRAMEADDR. Patch by Sasa Stankovic. 
llvm-svn: 132444
 2011-06-02 00:24:44 +00:00
Stuart Hastings
9a085fb9d8 Recommit 132404 with fixes. rdar://problem/5993888 
llvm-svn: 132424
 2011-06-01 21:33:14 +00:00
Stuart Hastings
4b33767382 Revert 132404 to appease a buildbot. rdar://problem/5993888 
llvm-svn: 132419
 2011-06-01 19:52:20 +00:00
Stuart Hastings
23f5ceda96 Add support for x86 CMPEQSS and friends. These instructions do a 
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404
 2011-06-01 17:17:45 +00:00
Jakob Stoklund Olesen
283a7e46b5 Fix PR10059 and future variations by handling all register subclasses. 
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398
 2011-06-01 15:32:10 +00:00
Stuart Hastings
fdc9e4af68 FGETSIGN support for x86, using movmskps/pd. Will be enabled with a 
patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388
 2011-06-01 04:39:42 +00:00
Bruno Cardoso Lopes
9231127d37 Fix uninitialized variables and silence warnings 
llvm-svn: 132355
 2011-05-31 20:25:26 +00:00
Richard Osborne
660fe84614 Fix 80 column violations. 
llvm-svn: 132341
 2011-05-31 16:30:33 +00:00
Richard Osborne
4293c93896 Add XCore intrinsic for crc8. 
llvm-svn: 132340
 2011-05-31 16:24:49 +00:00
Richard Osborne
34a4652dcd Add XCore intrinsic for crc32. 
llvm-svn: 132336
 2011-05-31 14:47:36 +00:00
Bruno Cardoso Lopes
0bdb365634 Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value 
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324
 2011-05-31 03:33:27 +00:00
Bruno Cardoso Lopes
728ea362c3 This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, 
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
 2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
f6fa29e7a1 This patch implements the thread local storage. Implemented are General 
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
 2011-05-31 02:53:58 +00:00
Rafael Espindola
33f7d7f9fa Use the dwarf->llvm mapping to print register names in the cfi 
directives.

Fixes PR9826.

llvm-svn: 132317
 2011-05-30 20:20:15 +00:00
Rafael Espindola
13607c5e91 Split ppc dwarf regnums into ppc64 and ppc32 flavours. 
llvm-svn: 132315
 2011-05-30 18:24:44 +00:00
Rafael Espindola
5917c1f6ec Introduce the DwarfRegAlias class for declaring that two registers have the 
same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

llvm-svn: 132314
 2011-05-30 17:49:59 +00:00
Rafael Espindola
00ba4a56e0 Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they are 
subregisters of the 64 bit ones.

llvm-svn: 132313
 2011-05-30 16:04:54 +00:00
Rafael Espindola
33338e912b Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_piece 
and for now the generic dwarf emission will automatically use the superregister
numbers.

llvm-svn: 132312
 2011-05-30 15:56:04 +00:00
John McCall
64ff21faa7 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

Take 2, now with more basic competence.

llvm-svn: 132295
 2011-05-29 19:50:32 +00:00
John McCall
ffdb2d5e70 I didn't mean to commit these residues of a personal project. 
llvm-svn: 132293
 2011-05-29 19:41:56 +00:00
John McCall
46c7b963b2 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

llvm-svn: 132291
 2011-05-29 19:39:04 +00:00
Rafael Espindola
bfde930279 Fix to match the dwarf register numbers that gdb uses. 
llvm-svn: 132278
 2011-05-29 03:58:16 +00:00
Rafael Espindola
06c8318a60 Dwarf register 0 is r0, remove incorrect entries. 
llvm-svn: 132276
 2011-05-29 03:17:01 +00:00
Rafael Espindola
51a8fe13bc Remove the dwarf numbers from the D registers. They don't have dwarf numbers 
and should probably be encoded as

DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33

llvm-svn: 132274
 2011-05-29 02:21:01 +00:00
Cameron Zwarich
72e034c331 Fix ARM fast isel to correctly flag memory operands to stores. This fixes 
-verify-machineinstrs failures on several tests.

llvm-svn: 132268
 2011-05-28 20:34:49 +00:00
Bruno Cardoso Lopes
6d5e369a10 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

llvm-svn: 132248
 2011-05-28 04:07:29 +00:00
Eric Christopher
a2fa6edef9 This actually starts at offset 0, not 1. 
llvm-svn: 132246
 2011-05-28 03:16:22 +00:00
Akira Hatanaka
45b3f52c41 Change the set of callee-saved registers for non-MIPS32 architectures specified 
in MipsRegisterInfo::getCalleeSavedRegs so that both registers paired for a
double precision register get saved.

 

llvm-svn: 132243
 2011-05-28 01:41:05 +00:00
Eric Christopher
000dd7d0e6 Implement the 'M' output modifier for arm inline asm. This is fairly 
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939

llvm-svn: 132242
 2011-05-28 01:40:44 +00:00
Akira Hatanaka
1590e4eab1 Define a wrapper node for target constant nodes (tglobaladdr, etc.). 
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
 2011-05-28 01:07:07 +00:00
Rafael Espindola
707fa44bc0 Add 132187 back now that the real problem is fixed. 
llvm-svn: 132238
 2011-05-28 00:24:37 +00:00
Cameron Zwarich
cd3c1b5829 Fix the remaining atomic intrinsics to use the right register classes on Thumb2, 
and add some basic tests for them.

llvm-svn: 132235
 2011-05-27 23:54:00 +00:00
Bruno Cardoso Lopes
93eae0fd19 ARM asm parser wasn't able to parse a "mov" instruction while in Thumb 
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

llvm-svn: 132233
 2011-05-27 23:46:09 +00:00
Rafael Espindola
8ed6285c8d It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check. 
llvm-svn: 132230
 2011-05-27 23:36:02 +00:00
Cameron Zwarich
ded03d4e24 Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass() 
was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.

llvm-svn: 132225
 2011-05-27 22:26:04 +00:00
Rafael Espindola
2230168a0f Make size computation less brittle. 
llvm-svn: 132222
 2011-05-27 22:05:41 +00:00
Evan Cheng
0fcb465bab Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789 
llvm-svn: 132211
 2011-05-27 20:11:27 +00:00