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4440 Commits

Author SHA1 Message Date
Johnny Chen
0da4c8bfec Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. 
llvm-svn: 129451
 2011-04-13 16:56:08 +00:00
Cameron Zwarich
86333383eb Fix a typo. 
llvm-svn: 129429
 2011-04-13 06:39:16 +00:00
Johnny Chen
5ae9980472 Add sanity check for Ld/St Dual forms of Thumb2 instructions. 
rdar://problem/9273947

llvm-svn: 129411
 2011-04-12 23:31:00 +00:00
Jakob Stoklund Olesen
b2c47a2087 Add @earlyclobber constraints to the writeback register of all ARM store instructions. 
The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

llvm-svn: 129409
 2011-04-12 23:27:48 +00:00
Johnny Chen
e3c070e904 The Thumb2 RFE instructions need to have their second halfword fully specified. 
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391
 2011-04-12 21:41:51 +00:00
Johnny Chen
4450794a69 Add bad register checks for Thumb2 Ld/St instructions. 
rdar://problem/9269047

llvm-svn: 129387
 2011-04-12 21:17:51 +00:00
Johnny Chen
4435fc93c9 The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23} 
be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.

llvm-svn: 129377
 2011-04-12 18:48:00 +00:00
Johnny Chen
aaaa46cee2 Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 
llvm-svn: 129365
 2011-04-12 17:09:04 +00:00
Cameron Zwarich
c05412175e Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM 
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

llvm-svn: 129345
 2011-04-12 02:24:17 +00:00
Johnny Chen
58713f0ec2 A8.6.16 B 
Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681

llvm-svn: 129325
 2011-04-12 00:14:49 +00:00
Johnny Chen
443a6902bf Thumb disassembler was erroneously rejecting "blx sp" instruction. 
rdar://problem/9267838

llvm-svn: 129320
 2011-04-11 23:33:30 +00:00
Johnny Chen
77f484c5df Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265

llvm-svn: 129298
 2011-04-11 21:14:35 +00:00
Owen Anderson
b8c2fc6d09 Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit. 
llvm-svn: 129294
 2011-04-11 20:12:19 +00:00
Johnny Chen
77dc5a7187 Trivial comment fix. 
llvm-svn: 129288
 2011-04-11 18:51:50 +00:00
Johnny Chen
b07cb8fee1 Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.

llvm-svn: 129286
 2011-04-11 18:34:12 +00:00
Kevin Enderby
6e09a5d065 Adding support for printing operands symbolically to llvm's public 'C' 
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284
 2011-04-11 18:08:50 +00:00
Jay Foad
0d5ca4cf44 Don't include Operator.h from InstrTypes.h. 
llvm-svn: 129271
 2011-04-11 09:35:34 +00:00
Matt Beaumont-Gay
16d2e58f1d Fix an apparent typo that made GCC complain 
llvm-svn: 129160
 2011-04-08 21:59:49 +00:00
Evan Cheng
bc053100af Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
llvm-svn: 129152
 2011-04-08 21:37:21 +00:00
Johnny Chen
18f79bbaca Check opcoe (dmb, dsb) instead of bitfields matching. 
llvm-svn: 129148
 2011-04-08 20:03:46 +00:00
Johnny Chen
e2464aa24a Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565

llvm-svn: 129147
 2011-04-08 19:41:22 +00:00
Johnny Chen
5b7854afa5 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634

llvm-svn: 129146
 2011-04-08 19:18:07 +00:00
Jim Grosbach
5e0618da1a Mark hasExtraDefRegAllocReq=1 on LDRD. 
The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.

rdar://9244161

llvm-svn: 129144
 2011-04-08 18:47:05 +00:00
Johnny Chen
16ed2c18a0 Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117
 2011-04-08 00:29:09 +00:00
Evan Cheng
9049eb2113 Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
llvm-svn: 129107
 2011-04-07 20:31:12 +00:00
Mon P Wang
9aa67ff50a Fixed encoding for VEXTqf 
llvm-svn: 129101
 2011-04-07 19:56:12 +00:00
Johnny Chen
5d23dd2116 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.

llvm-svn: 129098
 2011-04-07 19:28:58 +00:00
Johnny Chen
7198a60b9a Add sanity checking for invalid register encodings for saturating instructions. 
llvm-svn: 129096
 2011-04-07 19:02:08 +00:00
Johnny Chen
ecc113f223 Add some more comments about checkings of invalid register numbers. 
And two test cases.

llvm-svn: 129090
 2011-04-07 18:33:19 +00:00
Tanya Lattner
3deb96fad7 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
llvm-svn: 129074
 2011-04-07 15:24:20 +00:00
Johnny Chen
4c81015af7 Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844

llvm-svn: 129050
 2011-04-07 01:37:34 +00:00
Johnny Chen
1f028bb23e The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047
 2011-04-07 01:05:52 +00:00
Evan Cheng
859dff2c87 Change -arm-divmod-libcall to a target neutral option. 
llvm-svn: 129045
 2011-04-07 00:58:44 +00:00
Johnny Chen
523f8f38f7 Should also check SMLAD for invalid register values. 
rdar://problem/9246650

llvm-svn: 129042
 2011-04-07 00:50:25 +00:00
Owen Anderson
37b60bdf09 Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB. 
llvm-svn: 129038
 2011-04-06 23:35:59 +00:00
Owen Anderson
7f766b61a1 Cleanups from Jim: remove redundant constraints and a dead FIXME. 
llvm-svn: 129036
 2011-04-06 22:45:55 +00:00
Jim Grosbach
0510dc2765 Tidy up. 
llvm-svn: 129034
 2011-04-06 22:35:47 +00:00
Johnny Chen
81aa7d84be A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^

llvm-svn: 129033
 2011-04-06 22:14:48 +00:00
Johnny Chen
96fd9620c8 A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027
 2011-04-06 20:49:02 +00:00
Johnny Chen
b3130a03a7 Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015
 2011-04-06 18:27:46 +00:00
Johnny Chen
765dec3867 Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
 2011-04-06 01:18:32 +00:00
Owen Anderson
b59504a1a1 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding. 
llvm-svn: 128965
 2011-04-05 23:55:28 +00:00
Johnny Chen
48b39632aa Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register 
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

llvm-svn: 128958
 2011-04-05 23:28:00 +00:00
Bob Wilson
89dce9ab06 Clean up some code for clarity. 
llvm-svn: 128953
 2011-04-05 23:03:25 +00:00
Owen Anderson
c8ceb7246f Revert r128946 while I figure out why it broke the buildbots. 
llvm-svn: 128951
 2011-04-05 23:03:06 +00:00
Johnny Chen
359b9a2331 A7.3 register encoding 
Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

llvm-svn: 128949
 2011-04-05 22:57:07 +00:00
Owen Anderson
809f1a74d1 Give RSBS and RSCS the pseudo treatment. 
llvm-svn: 128946
 2011-04-05 22:42:54 +00:00
Johnny Chen
cf11408b65 ARM disassembler was erroneously accepting an invalid RSC instruction. 
Added checks for regs which should not be 15.

rdar://problem/9237734

llvm-svn: 128945
 2011-04-05 22:18:07 +00:00
Johnny Chen
6e1367d5dd ARM disassembler was erroneously accepting an invalid LSL instruction. 
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

llvm-svn: 128941
 2011-04-05 21:49:44 +00:00
Owen Anderson
b73d1741c6 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. 
llvm-svn: 128940
 2011-04-05 21:48:57 +00:00