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1724 Commits

Author SHA1 Message Date
Nate Begeman
10b97ea32f Handle instructions which need to be #defines for the purpose of capturing constant arguments 
Handle extract hi/lo with common code

llvm-svn: 105666
 2010-06-09 01:09:00 +00:00
Bruno Cardoso Lopes
255fda615d Reapply r105521, this time appending "LLU" to 64 bit 
immediates to avoid breaking the build.

llvm-svn: 105652
 2010-06-08 22:51:23 +00:00
Nate Begeman
c470186332 Fix a valgrind error. 
llvm-svn: 105600
 2010-06-08 07:11:17 +00:00
Nate Begeman
8df074e074 Refine BuiltinsARM.def types a bit, we should do a better job of this to save some c++ code in CGBuiltins. 
llvm-svn: 105598
 2010-06-08 06:01:16 +00:00
Nate Begeman
77a2b1b8b4 ARM NEON: 
fix vcvt naming
handle vdup, vcombine with generic vector code

llvm-svn: 105588
 2010-06-08 00:14:42 +00:00
Nate Begeman
477813692f clang codegen support 
llvm-svn: 105531
 2010-06-07 16:00:37 +00:00
Chris Lattner
33d0622cdc revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
b05131d907 Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.

llvm-svn: 105521
 2010-06-05 03:53:24 +00:00
Bruno Cardoso Lopes
b811561aac Teach tablegen to support 'defm' inside multiclasses. 
llvm-svn: 105519
 2010-06-05 02:11:52 +00:00
Nate Begeman
7a41bddd2c Handle multi-vector returns and args. 
llvm-svn: 105496
 2010-06-04 22:53:30 +00:00
Nate Begeman
60df12eda6 Additional fixes to BuiltinsARM.def generator, on to clang codegen. 
llvm-svn: 105488
 2010-06-04 21:36:00 +00:00
Nate Begeman
8275ffe1df Progress on generating BuiltinsARM.def, still some duplicates to work out. 
llvm-svn: 105461
 2010-06-04 07:11:25 +00:00
Nate Begeman
766330952e BuiltinsARM.def emitter, still needs a substantial bit of tweaking to lighten the load on clang. 
llvm-svn: 105456
 2010-06-04 01:26:15 +00:00
Nate Begeman
b5c41fee97 Mangle __builtin_neon_* names appropriately. 
Add skeleton of support for emitting the list of prototypes for BuiltinsARM.def

llvm-svn: 105443
 2010-06-04 00:21:41 +00:00
Nate Begeman
6483dc5067 Add some additional capabilities to the neon emitter 
llvm-svn: 105416
 2010-06-03 21:35:22 +00:00
Dale Johannesen
891a19d5ae Early implementation of tail call for ARM. 
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413
 2010-06-03 21:09:53 +00:00
Nate Begeman
86df2ed097 arm_neon.h now makes it through clang and generates appropriate code for those functions which can use 
generic vector operators rather than __builtin_neon_*

llvm-svn: 105380
 2010-06-03 04:04:09 +00:00
Nate Begeman
d0fe2c84d7 arm_neon.h emitter now mostly complete for the purposes of initial testing. 
llvm-svn: 105349
 2010-06-02 21:53:00 +00:00
Duncan Sands
67ba22b8e9 Pacify recent gcc: remove a pointless const qualifier. 
llvm-svn: 105318
 2010-06-02 08:37:30 +00:00
Nate Begeman
8c69aba08d Checkpoint; handle 'int' and 'void' correctly 
llvm-svn: 105316
 2010-06-02 07:14:28 +00:00
Nate Begeman
701f6c86e0 Emit full function prototypes. Definitions & typedefs to come. 
llvm-svn: 105315
 2010-06-02 06:17:19 +00:00
Nate Begeman
febb87a5c1 Checkpoint arm_neon.h generation with tablegen 
llvm-svn: 105307
 2010-06-02 00:34:55 +00:00
Alexis Hunt
9674fb4293 Fix comment 
llvm-svn: 105297
 2010-06-01 23:29:39 +00:00
Alexis Hunt
bdfc4b7cd0 Allow for creation of clang DeclNodes tables. 
The StmtNodes generator has been generalized to allow for the
creation of DeclNodes tables as well, and another emitter was
added for DeclContexts.

llvm-svn: 105164
 2010-05-30 07:21:42 +00:00
Jakob Stoklund Olesen
847b5eb54a Emit TargetRegisterInfo::composeSubRegIndices(). 
Also verify that all subregister indices compose unambiguously.

llvm-svn: 105064
 2010-05-28 23:48:31 +00:00
Nate Begeman
eb1028094c Comment out some code in prep for actual .td file checkpoint. 
llvm-svn: 104927
 2010-05-28 02:19:08 +00:00
Eli Friedman
f73aa6f0dc Fix build breakage. 
llvm-svn: 104912
 2010-05-28 01:15:28 +00:00
Nate Begeman
afef35118d Add support to tablegen for auto-generating arm_neon.h from a tablegen description 
of the intrinsics.  The goal is to auto-generate both support for GCC-style (vector)
and ARM-style (struct of vector) intrinsics.

This is work in progress, but will be completed soon.

llvm-svn: 104910
 2010-05-28 01:08:32 +00:00
Dan Gohman
bf1e648394 Simplify raw_ostream usage. 
llvm-svn: 104874
 2010-05-27 19:48:08 +00:00
Dan Gohman
3a54acdc12 Minor code simplification. 
llvm-svn: 104845
 2010-05-27 16:25:05 +00:00
Daniel Dunbar
0d29870989 AsmMatcher: Ensure classes are totally ordered, so we can std::sort them reliably. 
llvm-svn: 104806
 2010-05-27 05:31:32 +00:00
Jakob Stoklund Olesen
ee3ac9b299 Check that inherited subregisters all have a direct SubRegIndex. 
llvm-svn: 104755
 2010-05-26 22:15:07 +00:00
Jakob Stoklund Olesen
1c0aa5f14a Add StringRef::compare_numeric and use it to sort TableGen register records. 
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745
 2010-05-26 21:47:28 +00:00
Jakob Stoklund Olesen
bf22a695bd Suppress emmission of empty subreg/superreg/alias sets. 
llvm-svn: 104741
 2010-05-26 21:35:55 +00:00
Jakob Stoklund Olesen
83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
 2010-05-26 17:27:12 +00:00
Jakob Stoklund Olesen
0fefdf4d2a Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

llvm-svn: 104660
 2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
a2f0c34e41 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
 2010-05-26 00:28:19 +00:00
Jakob Stoklund Olesen
41388819f1 Drop the SuperregHashTable. It is essentially the same as SubregHashTable. 
llvm-svn: 104650
 2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen
9210d3b189 Print symbolic SubRegIndex names on machine operands. 
llvm-svn: 104628
 2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
6e7961be11 Ignore NumberHack and give each SubRegIndex instance a unique enum value instead. 
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

llvm-svn: 104615
 2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
d1f4d14609 Switch SubRegSet to using symbolic SubRegIndices 
llvm-svn: 104571
 2010-05-24 23:03:18 +00:00
Chris Lattner
6ea2f4d4cc diaggroup categories should take precedence over diag-specific groups. 
llvm-svn: 104567
 2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
3a19b732d8 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
 2010-05-24 21:46:58 +00:00
Jakob Stoklund Olesen
9a54fec092 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
 2010-05-24 14:48:12 +00:00
Daniel Dunbar
ee525943d8 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
llvm-svn: 104452
 2010-05-22 21:02:29 +00:00
Daniel Dunbar
64807873ec tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor 
it.

llvm-svn: 104270
 2010-05-20 20:20:32 +00:00
Alexis Hunt
0774d14741 Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macro 
Also rename ABSTRACT to ABSTRACT_STMT

llvm-svn: 104018
 2010-05-18 06:22:50 +00:00
Evan Cheng
2af2c9fa14 Added a QQQQ register file to model 4-consecutive Q registers. 
llvm-svn: 103760
 2010-05-14 02:13:41 +00:00
Evan Cheng
775549c9e7 Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. 
llvm-svn: 103746
 2010-05-13 23:55:47 +00:00
Chandler Carruth
d37bcf5e2c Update tablegen to generate shorts instead of chars for subgroup arrays. 
llvm-svn: 103704
 2010-05-13 07:43:47 +00:00