39092 Commits

Author SHA1 Message Date
Dan Gohman
1ccf40774e Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.

llvm-svn: 106296
2010-06-18 18:13:55 +00:00
Dale Johannesen
9f18fc3fa2 Last round of changes for ARM tail calls.
Not turning them on yet.

llvm-svn: 106295
2010-06-18 18:13:11 +00:00
Bob Wilson
9af2272272 Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,
so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore
an instruction because it is a branch, it should not check if the branch is
predicated.

This case (when IgnoreBr is true) is only relevant from IfConvertTriangle,
where new branches are inserted after the block has been copied and predicated.
If the original branch is not removed, we end up with multiple conditional
branches (possibly conflicting) at the end of the block.  Aside from any
immediate errors resulting from that, this confuses the AnalyzeBranch functions
so that the branches are not analyzable.  That in turn causes the IfConverter to
think that the "Simple" pattern can be applied, and things go downhill fast
because the "Simple" pattern does _not_ apply if the block can fall through.

This is pretty fragile.  If there are other degenerate cases where AnalyzeBranch
fails, but where the block may still fall through, the IfConverter should not
perform its "Simple" if-conversion.  But, I don't know how to do that with the
current AnalyzeBranch interface, so for now, the best thing seems to be to
avoid creating branches that AnalyzeBranch cannot handle.

Evan, please review!

llvm-svn: 106291
2010-06-18 17:07:23 +00:00
Jakob Stoklund Olesen
6c387d99ca Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

llvm-svn: 106289
2010-06-18 16:49:33 +00:00
Dan Gohman
0422fad3a6 Don't bother calling releaseMemory before destroying the DominatorTreeBase.
llvm-svn: 106287
2010-06-18 16:09:11 +00:00
Dan Gohman
07dc65e0b5 Minor code simplifications.
llvm-svn: 106286
2010-06-18 16:00:29 +00:00
Dan Gohman
6c6e9a45ff Give NamedRegionTimer an Enabled flag, allowing all its clients to
switch from this:

  if (TimePassesIsEnabled) {
    NamedRegionTimer T(Name, GroupName);
    do_something();
  } else {
    do_something(); // duplicate the code, this time without a timer!
  }

to this:

  {
    NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled);
    do_something();
  }

llvm-svn: 106285
2010-06-18 15:56:31 +00:00
Dan Gohman
6670a7edea Don't replace the old Ordering object with a new one; just clear()
the old one.

llvm-svn: 106284
2010-06-18 15:40:58 +00:00
Dan Gohman
d3b13d1a68 Don't call clear() on DbgInfo when it's going to be deleted anyway.
Don't replace the old DbgInfo with a new one when clear() on the
old one is sufficient.

llvm-svn: 106283
2010-06-18 15:36:18 +00:00
Dan Gohman
e9dfb84007 Change UpdateNodeOperands' operand and return value from SDValue to
SDNode *, since it doesn't care about the ResNo value.

llvm-svn: 106282
2010-06-18 15:30:29 +00:00
Dan Gohman
e20e668c7e Remove getIntegerSCEV; it's redundant with getConstant, and getConstant
is more consistent with the ConstantInt API.

llvm-svn: 106281
2010-06-18 14:33:50 +00:00
Dan Gohman
9443053ec4 Delete unused variables.
llvm-svn: 106280
2010-06-18 14:32:32 +00:00
Dan Gohman
0b5b93b20d Eliminate unnecessary uses of getZExtValue().
llvm-svn: 106279
2010-06-18 14:22:04 +00:00
Dan Gohman
22ff84372b isValueValidForType can be a static member function.
llvm-svn: 106278
2010-06-18 14:01:07 +00:00
Eric Christopher
e60cfc56b0 Some assorted isTwoAddress -> Constraints cleanup.
llvm-svn: 106273
2010-06-18 02:41:19 +00:00
Dan Gohman
7bd41176cc Handle execution entrypoints with non-integer return types.
Fix from Russel Power in PR7284.

llvm-svn: 106271
2010-06-18 02:01:10 +00:00
Dan Gohman
e375e96f0d Disable indvars on loops when LoopSimplify form is not available.
This fixes PR7333.

llvm-svn: 106267
2010-06-18 01:35:11 +00:00
Dan Gohman
9d7cf23808 Don't maintain a set of deleted nodes; instead, use a HandleSDNode
to track a node over CSE events. This fixes PR7368.

llvm-svn: 106266
2010-06-18 01:24:29 +00:00
Bruno Cardoso Lopes
ea44492375 Add {mix,max}{ss,sd}{rr,rm} AVX forms.
llvm-svn: 106264
2010-06-18 01:12:56 +00:00
Dan Gohman
8185674354 Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
which is faster, simpler, and less surprising.

llvm-svn: 106263
2010-06-18 01:05:21 +00:00
Dan Gohman
eab6b51039 Fix a typo in a comment.
llvm-svn: 106260
2010-06-18 00:53:08 +00:00
Dan Gohman
57046ca982 Handle ext(ext(x)) -> ext(x) immediately, since it's simple.
llvm-svn: 106256
2010-06-18 00:08:30 +00:00
Dan Gohman
1d9d93381a Simplify this code.
llvm-svn: 106254
2010-06-17 23:34:09 +00:00
Bruno Cardoso Lopes
4cbdbd5501 Use new tablegen resources in SSE tablegen code. This will
be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction

llvm-svn: 106251
2010-06-17 23:05:30 +00:00
Stuart Hastings
bd7194d21c Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243
2010-06-17 22:43:56 +00:00
Jim Grosbach
ac23214fd8 add missing break. inconsequential as the code shouldn't be reached, but
for correctness' sake, it should be there.

llvm-svn: 106229
2010-06-17 17:58:54 +00:00
Jim Grosbach
99b7091d9d Add entries for Expanding atomic intrinsics to libcalls. Just a placeholder
for the moment. The implementation of the libcall will follow.

Currently, the llvm-gcc knows when the intrinsics can be correctly handled by
the back end and only generates them in those cases, issuing libcalls directly
otherwise. That's too much coupling. The intrinsics should always be
generated and the back end decide how to handle them, be it with a libcall,
inline code, or whatever. This patch is a step in that direction.

rdar://8097623

llvm-svn: 106227
2010-06-17 17:50:54 +00:00
Jim Grosbach
f3f401f911 Thumb1 and any pre-v6 ARM target should use the libcall expansion of
ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.

llvm-svn: 106204
2010-06-17 02:02:03 +00:00
Jim Grosbach
0cdb6c563a ISD::MEMBARRIER should lower to a libcall (__sync_synchronize) if the target
sets the legalize action to Expand.

llvm-svn: 106203
2010-06-17 02:00:53 +00:00
Jim Grosbach
8d77e0298c simplify code a bit and add a more explanatory assert for cases that
previously would result in 'cannot yet select' errors.

llvm-svn: 106199
2010-06-17 01:37:00 +00:00
Jason Molenda
830bbc15f4 Add the entire range of DW_OP_lit[0..31], DW_OP_reg[0..31], and
DW_OP_breg[0..31] to Dwarf.h.

Add "DW_" prefix to the llvm::dwarf::*String methods which did not
already have them in Dwarf.cpp.

llvm-svn: 106197
2010-06-17 01:23:24 +00:00
Eric Christopher
bb75081f00 Hack to let the move lowering handle dynamic-no-pic absolute moves of
TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.
llvm-svn: 106194
2010-06-17 00:51:48 +00:00
Eric Christopher
b92292eb08 Update comment.
llvm-svn: 106191
2010-06-17 00:49:46 +00:00
Jim Grosbach
b5bea8fdba format and 80-column cleanup
llvm-svn: 106173
2010-06-16 23:45:49 +00:00
Jim Grosbach
f5107a8ada remove trailing whitespace
llvm-svn: 106164
2010-06-16 22:41:09 +00:00
Jakob Stoklund Olesen
a97220ab96 Don't attempt preserving conservative kill flags. We were doing it wrong.
This is before LiveVariables anyway, where these kill flags are recalculated.

llvm-svn: 106157
2010-06-16 22:11:08 +00:00
Bob Wilson
d81a716d59 Remove the hidden "neon-reg-sequence" option. The reg sequences are working
now, so there's no need to disable them.

llvm-svn: 106155
2010-06-16 21:34:01 +00:00
Eric Christopher
9c56c0a851 In progress on 32-bit addends.
llvm-svn: 106154
2010-06-16 21:32:38 +00:00
Jakob Stoklund Olesen
4f5d1d7004 Allow a register to be redefined multiple times in a basic block.
LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.

Here is an example of chained INSERT_SUBREGs that we can handle now:

68      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
                register: %reg1040 +[70,134:0)
76      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
                register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0)  0@78-(134) 1@70-(78)
84      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
                register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0)  0@86-(134) 1@70-(78) 2@78-(86)
92      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
                register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0)  0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)

rdar://problem/8096390

llvm-svn: 106152
2010-06-16 21:29:40 +00:00
Jim Grosbach
67b46d6303 A few more places where SCEVExpander bits need to skip over debug intrinsics
when iterating through instructions. Yet more work for rdar://7797940

llvm-svn: 106149
2010-06-16 21:13:38 +00:00
Daniel Dunbar
15c2792d21 MC/Mach-O: Rewrite atom association to be a final pass we do in Finish(), instead of tracking as part of emission.
- This allows sharing more code with the MCObjectStreamer.

llvm-svn: 106143
2010-06-16 20:04:32 +00:00
Daniel Dunbar
2c6d6693e2 MC: Simplify MCAssembler::isSymbolLinkerVisible to only take an MCSymbol.
llvm-svn: 106142
2010-06-16 20:04:29 +00:00
Daniel Dunbar
7631ddfec4 MC: Lift SwitchSection() and Finish() into MCObjectStreamer.
llvm-svn: 106141
2010-06-16 20:04:25 +00:00
Daniel Dunbar
d52ca1c3e5 MC: Factor out an MCObjectStreamer class, which will be shared by the concrete
object file format writers.

llvm-svn: 106140
2010-06-16 20:04:22 +00:00
Rafael Espindola
6ccafc9391 Make sure that simplify libcalls does not replace a call with one calling
convention with a new call with a different calling convention.

llvm-svn: 106134
2010-06-16 19:34:01 +00:00
Jim Grosbach
de52e401c9 add FIXME
llvm-svn: 106126
2010-06-16 18:45:08 +00:00
Bill Wendling
670df11fd6 Improve comment to include that the use of a preg is also verboten in this situation.
llvm-svn: 106119
2010-06-16 18:01:31 +00:00
Benjamin Kramer
01a44323f0 TODO--
llvm-svn: 106102
2010-06-16 15:47:00 +00:00
Benjamin Kramer
f600dc2eed simplify-libcalls: fold strncmp(x, y, 1) -> memcmp(x, y, 1)
The memcmp will be optimized further and even the pathological case
'strstr(x, "x") == x' generates optimal code now.

llvm-svn: 106097
2010-06-16 10:30:29 +00:00
Evan Cheng
46b89e05fd Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
llvm-svn: 106091
2010-06-16 07:35:02 +00:00