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14697 Commits

Author SHA1 Message Date
Daniel Dunbar
220bd809bf X86-64: Mark WINCALL and more tail call instructions as code gen only. 
llvm-svn: 108685
 2010-07-19 07:21:07 +00:00
Daniel Dunbar
fa2847103d X86: Mark some tail call pseduo instruction as code gen only. 
llvm-svn: 108684
 2010-07-19 07:21:04 +00:00
Daniel Dunbar
f228215d4f X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64]. 
llvm-svn: 108683
 2010-07-19 07:21:01 +00:00
Daniel Dunbar
3b0ff3bac3 MC/X86: We now match instructions like "incl %eax" correctly for the arch we are 
assembling; remove crufty custom cleanup code.

llvm-svn: 108681
 2010-07-19 06:14:54 +00:00
Daniel Dunbar
7a3565367a X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real. 
llvm-svn: 108680
 2010-07-19 06:14:49 +00:00
Daniel Dunbar
9409c3fbb2 X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode. 
llvm-svn: 108679
 2010-07-19 06:14:44 +00:00
Daniel Dunbar
f58b5d7ad0 TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher. 
- Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.

llvm-svn: 108677
 2010-07-19 05:44:09 +00:00
Daniel Dunbar
150021561c Target: Give the TargetAsmParser access to the TargetMachine. 
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.

llvm-svn: 108664
 2010-07-19 00:33:49 +00:00
Chris Lattner
be480fb7dc the stackifier is global! 
llvm-svn: 108626
 2010-07-17 17:42:04 +00:00
Chris Lattner
dac9788e6b doxygenify some comments. 
llvm-svn: 108625
 2010-07-17 17:40:51 +00:00
Jim Grosbach
270540da7b Add combiner patterns to more effectively utilize the BFI (bitfield insert) 
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.

llvm-svn: 108608
 2010-07-17 03:30:54 +00:00
Jim Grosbach
e52a4aff12 add BFI to getTargetNodeName() 
llvm-svn: 108603
 2010-07-17 01:50:57 +00:00
Jim Grosbach
5e095020ae Fix logic think-o 
llvm-svn: 108601
 2010-07-17 01:22:19 +00:00
Eric Christopher
00b8fa89c8 Remove unnecessary check that was subsumed into canRealignStack. 
llvm-svn: 108588
 2010-07-17 00:33:04 +00:00
Eric Christopher
033201e862 Make more explicit and add some currently disabled error messages for 
stack realignment on ARM.

Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.

llvm-svn: 108582
 2010-07-17 00:27:24 +00:00
Eric Christopher
cfd5cd156c Make comment a bit more clear as well as return statement since 
needsStackRealignment is currently checking the can conditions as well.

llvm-svn: 108581
 2010-07-17 00:25:41 +00:00
Jim Grosbach
749f4fca0a Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction 
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570
 2010-07-16 23:05:05 +00:00
Jakob Stoklund Olesen
44949b2e1b Remove the isMoveInstr() hook. 
llvm-svn: 108567
 2010-07-16 22:35:46 +00:00
Jakob Stoklund Olesen
24994a5d4c Avoid isMoveInstr when printing XCore pseudo-moves. 
llvm-svn: 108566
 2010-07-16 22:35:37 +00:00
Jakob Stoklund Olesen
c73aa71e90 Use MI.isCopy. 
llvm-svn: 108565
 2010-07-16 22:35:34 +00:00
Jakob Stoklund Olesen
d073973e61 Use a small local function for a single remaining late isMoveInstr call in 
Thumb2ITBlockPass.

llvm-svn: 108564
 2010-07-16 22:35:32 +00:00
Bill Wendling
e2833a21c2 Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and 
thus is a much more meaningful name.

llvm-svn: 108563
 2010-07-16 22:20:36 +00:00
Jakob Stoklund Olesen
41b1ea4fc9 Keep valgrind quiet. 
The isLive() method can read uninitialized memory, but it still gives correct
results.

llvm-svn: 108561
 2010-07-16 22:00:33 +00:00
Jakob Stoklund Olesen
9521e574f8 Emit COPY instead of FMR/FMSD instructions for floating point conversion on 
PowerPC.

llvm-svn: 108555
 2010-07-16 21:03:52 +00:00
Eli Friedman
616313e9c6 Add missing attributes to cpp backend. 
llvm-svn: 108547
 2010-07-16 18:47:20 +00:00
Dale Johannesen
80b46398ab Accept registers with P modifier. PR 5314. 
llvm-svn: 108545
 2010-07-16 18:35:46 +00:00
Jakob Stoklund Olesen
701cbc5c89 Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memory 
operands.

Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't
since missing memoperands should not affect correctness.

llvm-svn: 108540
 2010-07-16 18:22:00 +00:00
Jakob Stoklund Olesen
858d6bb512 Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill 
pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

llvm-svn: 108536
 2010-07-16 17:41:44 +00:00
Jakob Stoklund Olesen
5fbe7d869c Search for a free FP register instead of just assuming FP7 is not in use. 
llvm-svn: 108535
 2010-07-16 17:41:40 +00:00
Jakob Stoklund Olesen
d578c5af7e Allow x87 FP registers to be alive globally in a function. 
FP_REG_KILL instructions are still inserted, but can be disabled by passing
-live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly.

CFG edges are partioned into bundles where the x87 stack must be allocated
identically. Code is insertad at the end of each basic block that shuffles the
live FP registers to match the outgoing bundles expectations.

This fix is in preparation for some upcoming register allocator improvements
that may extend the live range of registers beyond a basic block, similar to
LICM. It also provides a nice runtime speedup if you are building with
-mfpmath=387.

llvm-svn: 108529
 2010-07-16 16:38:12 +00:00
Evan Cheng
ffbae6ad52 Split -enable-finite-only-fp-math to two options: 
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465
 2010-07-15 22:07:12 +00:00
Chris Lattner
5e03b135cb fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3, 
this fixes rdar://8192860.  Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.

llvm-svn: 108454
 2010-07-15 20:13:34 +00:00
Eli Friedman
fc1680a9af Random note about bswap. 
llvm-svn: 108396
 2010-07-15 02:20:38 +00:00
Jakob Stoklund Olesen
0a565bde90 Last COPY conversion. 
llvm-svn: 108387
 2010-07-14 23:58:21 +00:00
Bob Wilson
27e348cfa5 Remove restriction on NEON alignment values. Some of the NEON ld/st 
instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.

llvm-svn: 108386
 2010-07-14 23:54:43 +00:00
Jakob Stoklund Olesen
e3aafe4988 Use TargetOpcode::COPY instead of X86-native register copy instructions when 
lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.

llvm-svn: 108385
 2010-07-14 23:50:27 +00:00
Chris Lattner
fa93b779db fix indentation 
llvm-svn: 108368
 2010-07-14 23:04:59 +00:00
Benjamin Kramer
da3e6cdb26 Don't pass StringRef by reference. 
llvm-svn: 108366
 2010-07-14 22:38:02 +00:00
Chris Lattner
2793cb1bd6 Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h, 
patch by Michael Spencer!

llvm-svn: 108342
 2010-07-14 18:14:33 +00:00
Jim Grosbach
e2d1ecbe70 Improve 64-subtraction of immediates when parts of the immediate can fit 
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339
 2010-07-14 17:45:16 +00:00
Bob Wilson
f60d34bfad Add missing address register update to t2LDM_RET instruction. 
Patch by Brian Lucas. PR7636.

llvm-svn: 108332
 2010-07-14 16:02:13 +00:00
Eli Friedman
7175d7558d A couple potential optimizations inspired by comment 4 in PR6773. 
llvm-svn: 108328
 2010-07-14 06:58:26 +00:00
Evan Cheng
f6478f489d Fix for PR7193 was overly conservative. The only case where sibcall callee 
address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.

This fixes PR7610.

llvm-svn: 108327
 2010-07-14 06:44:01 +00:00
Bob Wilson
34f481e895 Add support for NEON VMVN immediate instructions. 
llvm-svn: 108324
 2010-07-14 06:31:50 +00:00
Bob Wilson
298c5c46c1 The bits in the cmode field of 32-bit VMOV immediate instructions all depend 
of the value of the immediate.

llvm-svn: 108323
 2010-07-14 06:30:44 +00:00
Chris Lattner
25b9b8f2fc fix a bug found by a warning I added to clang this morning. 
llvm-svn: 108309
 2010-07-14 01:57:17 +00:00
Bob Wilson
0f581a998c Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes. 
Radar 7373643.

llvm-svn: 108303
 2010-07-14 01:22:12 +00:00
Dan Gohman
18711b19c9 Don't propagate debug locations to instructions for materializing 
constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.

llvm-svn: 108302
 2010-07-14 01:07:44 +00:00
Bruno Cardoso Lopes
0616a418b6 Add AVX 256-bit compare instructions and a bunch of testcases 
llvm-svn: 108286
 2010-07-13 22:06:38 +00:00
Bob Wilson
7feb850d36 Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent 
NEON VMOV-immediate instructions.  This simplifies some things.

llvm-svn: 108275
 2010-07-13 21:16:48 +00:00