RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-04-12 12:33:17 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
21,554 Commits 6 Branches 6 Tags
Commit Graph

44 Commits

Author SHA1 Message Date
Evan Cheng
231b11ba87 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Evan Cheng
bd79f871a2 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG 
support which is fragile.
* Fixed a number of bugs.

llvm-svn: 24996
 2005-12-23 22:11:47 +00:00
Evan Cheng
54695fd38d Support for read / write from explicit registers with FlagVT type. 
llvm-svn: 24753
 2005-12-17 01:19:28 +00:00
Evan Cheng
ed205f20a5 * Added an explicit type field to ComplexPattern. 
* Renamed MatchingNodes to RootNodes.

llvm-svn: 24636
 2005-12-08 02:14:08 +00:00
Evan Cheng
d11d31e0bd Added support for ComplexPattern. These are patterns that require C++ pattern 
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.

llvm-svn: 24634
 2005-12-08 02:00:36 +00:00
Evan Cheng
cf4f349880 * Commit the fix (by Chris) for a tblgen type inferencing bug. 
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.

llvm-svn: 24587
 2005-12-04 08:18:16 +00:00
Nate Begeman
811a41a87c Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Nate Begeman
b79a074c0a Nuke CodeGenInstruction's ValueType member, it is no longer used. 
llvm-svn: 24556
 2005-12-01 00:12:04 +00:00
Nate Begeman
e4d7c1b7dd Add the new vector types to tablegen 
llvm-svn: 24514
 2005-11-29 06:19:38 +00:00
Chris Lattner
3727cc7ac0 Initialize this variable on all paths, fixing a crasher in windows. Thanks 
to JeffC for pointing this out.

llvm-svn: 24426
 2005-11-19 07:48:33 +00:00
Chris Lattner
a36ad00a9a Teach tblgen about instruction operands that have multiple MachineInstr 
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!

llvm-svn: 24424
 2005-11-19 07:05:57 +00:00
Chris Lattner
06c5e018ef Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately 
reflect what it is.
Convert some more code over to use it.

llvm-svn: 24072
 2005-10-28 22:49:02 +00:00
Chris Lattner
ee8c8e4562 Do not let getLegalValueTypes return a list with duplicates in it 
llvm-svn: 23723
 2005-10-14 03:54:49 +00:00
Chris Lattner
9c196b02fa force all instruction operands to be named. 
llvm-svn: 23358
 2005-09-14 21:13:50 +00:00
Chris Lattner
c19f24f3d7 Check that operands have unique names. REJECT instructions with broken operand 
lists: only don't parse them if they are entirely missing (sparcv9).

llvm-svn: 23355
 2005-09-14 21:05:02 +00:00
Chris Lattner
0dd99c9aaf Add a new Record::getValueAsCode method to mirror the other getValueAs* 
methods.  Use it to simplify some code.

llvm-svn: 23336
 2005-09-13 21:44:28 +00:00
Chris Lattner
e2fb8f3a77 Compute the value types that are natively supported by a target. 
llvm-svn: 23282
 2005-09-08 21:43:21 +00:00
Chris Lattner
497c012e54 spell this right 
llvm-svn: 23099
 2005-08-26 20:55:40 +00:00
Chris Lattner
6c4ea26961 spell this variable right 
llvm-svn: 23095
 2005-08-26 20:42:52 +00:00
Chris Lattner
b474a0ab06 Expose a new flag to TargetInstrInfo 
llvm-svn: 23094
 2005-08-26 20:40:46 +00:00
Chris Lattner
20c1c4cf07 Split register class "Methods" into MethodProtos and MethodBodies 
llvm-svn: 22928
 2005-08-19 19:12:51 +00:00
Chris Lattner
341308dc6b Read the namespace field from register classes 
llvm-svn: 22918
 2005-08-19 18:45:20 +00:00
Chris Lattner
5ac318c67b Fix a problem jeffc noticed 
llvm-svn: 22903
 2005-08-19 06:16:04 +00:00
Chris Lattner
d03fa09ce7 Figure out how many operands each instruction has, keep track of whether 
or not it's variable.

llvm-svn: 22885
 2005-08-18 23:38:41 +00:00
Misha Brukman
960a8d47d7 Remove trailing whitespace 
llvm-svn: 21428
 2005-04-22 00:00:37 +00:00
Chris Lattner
f78580dcec Refactor code for numbering instructions into CodeGenTarget. 
llvm-svn: 19758
 2005-01-22 18:58:51 +00:00
Chris Lattner
2aef5783b0 Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. 
llvm-svn: 19243
 2005-01-02 02:29:04 +00:00
Misha Brukman
a87a2029e4 * Add option to read isLittleEndianEncoding for InstrInfo classes 
* Doxygen-ify some function comments

llvm-svn: 16974
 2004-10-14 05:50:43 +00:00
Chris Lattner
9a649a5c05 Add initial support for variants. This just parses the new format, no 
functionality is added

llvm-svn: 16636
 2004-10-03 19:34:31 +00:00
Nate Begeman
bbf7945b61 Add support for the isLoad and isStore flags, needed by the instruction scheduler 
llvm-svn: 16554
 2004-09-28 21:01:45 +00:00
Chris Lattner
7a941d7691 Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG 
llvm-svn: 16553
 2004-09-28 18:38:01 +00:00
Chris Lattner
e35741184e Alignment is now in bits. 
llvm-svn: 15976
 2004-08-21 20:15:25 +00:00
Chris Lattner
e88b8e3471 Make alignment be in bits, just like size is 
llvm-svn: 15969
 2004-08-21 20:00:36 +00:00
Chris Lattner
75ca702833 Support "Methods" in register classes in CodgeGenRegisterClass 
llvm-svn: 15965
 2004-08-21 19:21:21 +00:00
Chris Lattner
c33c1c8dca Start parsing register classes into a more structured form 
llvm-svn: 15961
 2004-08-21 04:05:00 +00:00
Chris Lattner
820f674293 Read in declared reg sizes 
llvm-svn: 15960
 2004-08-21 02:24:57 +00:00
Chris Lattner
892fc12546 Use CodeGenRegister class to make reading in of register information more 
systematic.

llvm-svn: 15805
 2004-08-16 01:10:21 +00:00
Chris Lattner
d7240cdb18 Make the AsmWriter a first-class tblgen object. Allow targets to specify 
name of the generated asmwriter class, and the name of the format string.

llvm-svn: 15747
 2004-08-14 22:50:53 +00:00
Chris Lattner
a88aec6972 Start parsing more information from the Operand information 
llvm-svn: 15644
 2004-08-11 02:22:39 +00:00
Chris Lattner
c8ac0bf803 Remove special case hacks 
llvm-svn: 15643
 2004-08-11 01:53:58 +00:00
Chris Lattner
350b76be29 Parse the operand list of the instruction. We currently support register and immediate operands. 
llvm-svn: 15390
 2004-08-01 07:42:39 +00:00
Chris Lattner
a983ac4661 Initial cut at an asm writer emitter. So far, this only handles emission of 
instructions, and only instructions that take no operands at that!

llvm-svn: 15386
 2004-08-01 05:59:33 +00:00
Chris Lattner
09d6e317a8 Add, and start using, the CodeGenInstruction class. This class represents 
an instance of the Instruction tablegen class.

llvm-svn: 15385
 2004-08-01 05:04:00 +00:00
Chris Lattner
07525455a6 Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h) 
llvm-svn: 15382
 2004-08-01 04:04:35 +00:00