2154 Commits

Author SHA1 Message Date
David Goodwin
36a5b02e4f Use NEON for single-precision int<->FP conversions.
llvm-svn: 78604
2009-08-10 22:17:39 +00:00
Evan Cheng
f0bb0f5204 Handle the constantfp created during post-legalization dag combiner phase.
llvm-svn: 78594
2009-08-10 20:25:59 +00:00
Dan Gohman
fe048746c2 Add nounwind keywords.
llvm-svn: 78568
2009-08-10 16:48:40 +00:00
Chris Lattner
cc70d578be Make the big switch: Change MCSectionMachO to represent a section *semantically*
instead of syntactically as a string.  This means that it keeps track of the 
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and 
"attribute(section)", so we should now start getting errors about invalid 
section attributes from the compiler instead of the assembler on darwin.

Still todo: 
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
   S_GB_ZEROFILL segment type?

llvm-svn: 78547
2009-08-10 01:39:42 +00:00
Bob Wilson
8b13d5c8e3 Add tests for Neon VZIP and VUZP instructions.
llvm-svn: 78529
2009-08-09 06:48:29 +00:00
Bob Wilson
06b61e2598 Add a test for Neon VTRN instructions.
llvm-svn: 78528
2009-08-09 06:30:46 +00:00
Eric Christopher
40031ed766 Add crc32 instruction and intrinsics. Add a new class of prefix
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.

New test.

llvm-svn: 78508
2009-08-08 21:55:08 +00:00
Jakob Stoklund Olesen
ed8219b3a1 Add support for READCYCLECOUNTER in Blackfin back-end.
llvm-svn: 78506
2009-08-08 21:42:22 +00:00
Jakob Stoklund Olesen
ee9c202c91 Don't build illegal ops in DAGCombiner::SimplifyBinOpWithSameOpcodeHands().
Blackfin supports and/or/xor on i32 but not on i16. Teach
DAGCombiner::SimplifyBinOpWithSameOpcodeHands to not produce illegal nodes
after legalize ops.

llvm-svn: 78497
2009-08-08 20:42:17 +00:00
Jakob Stoklund Olesen
f73b30b329 Simplify RegScavenger::forward a bit more.
Verify that early clobber registers and their aliases are not used.

All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.

The included test case is from PR4686. It has behaviour that was dependent on the order of operands.

llvm-svn: 78465
2009-08-08 13:18:47 +00:00
Anton Korobeynikov
e02d21a125 Do not generate 32-bit call on win64 when imm does not fit
llvm-svn: 78443
2009-08-07 23:59:21 +00:00
Chris Lattner
2a218ebe6a rename test
llvm-svn: 78441
2009-08-07 23:57:30 +00:00
Chris Lattner
bb68377453 merge a bunch of tests together into one, convert to filecheck which
is more tolerant of whitespace differences.

llvm-svn: 78439
2009-08-07 23:56:42 +00:00
Bob Wilson
a2913fe5f5 Convert more Neon tests to use FileCheck.
llvm-svn: 78433
2009-08-07 23:45:02 +00:00
David Goodwin
c0fe95d8ce Make NEON single-precision FP support the default for cortex-a8 (again).
llvm-svn: 78430
2009-08-07 23:32:33 +00:00
Anton Korobeynikov
9b52601704 2 more vdup.32 cases
llvm-svn: 78419
2009-08-07 22:36:50 +00:00
Evan Cheng
2bdb247c12 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
llvm-svn: 78410
2009-08-07 21:19:10 +00:00
Evan Cheng
0dab4cc8a0 Fix support to use NEON for single precision fp math.
llvm-svn: 78397
2009-08-07 19:30:41 +00:00
Evan Cheng
a565450757 Another coalescer bug. When a dead copy is eliminated, transfer the kill to a def of the exact register rather than a super-register.
llvm-svn: 78376
2009-08-07 07:14:14 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
2009-08-07 00:34:42 +00:00
Dale Johannesen
44233430ea Add the testcase from PR 4668. This works at the
moment, but it's a fragile area.

llvm-svn: 78358
2009-08-07 00:04:42 +00:00
Dale Johannesen
3cdd3d3633 Fix PR 4626, a crash in branch folding after OptimizeBlock
produced a CFG it wasn't prepared for.

llvm-svn: 78351
2009-08-06 22:56:40 +00:00
Bob Wilson
bd7627b23e Implement Neon VST[234] operations.
llvm-svn: 78330
2009-08-06 18:47:44 +00:00
Bob Wilson
5cbc89337b Fix incorrect intrinsic declarations.
llvm-svn: 78329
2009-08-06 18:46:26 +00:00
Dan Gohman
8456ae6bc8 Tidy up this testcase.
llvm-svn: 78322
2009-08-06 17:11:55 +00:00
Chris Lattner
c5342dabc4 reduce testcase.
llvm-svn: 78315
2009-08-06 16:14:33 +00:00
Dan Gohman
904eb68a6a Remove an over-aggressive assert. Functions with empty struct return
types don't have any return values, from CodeGen's perspective.
This fixes PR4688.

llvm-svn: 78311
2009-08-06 15:07:58 +00:00
Anton Korobeynikov
9c59e1a990 Add tests for X86-64 code model handling. Small and kernel for now.
llvm-svn: 78300
2009-08-06 12:25:20 +00:00
Dan Gohman
668a0ff5ef Fix a bug in x86's PreprocessForRMW logic that was exposed
by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.

llvm-svn: 78297
2009-08-06 09:22:57 +00:00
Dan Gohman
01b8a3593b Fix a few places in DAGCombiner that were creating all-ones-bits
and high-bits values in ways that weren't correct for integer
types wider than 64 bits. This fixes a miscompile in
PPMacroExpansion.cpp in clang on x86-64.

llvm-svn: 78295
2009-08-06 09:18:59 +00:00
Chris Lattner
53626c5606 this passes.
llvm-svn: 78281
2009-08-06 03:55:49 +00:00
Sanjiv Gupta
16ccd693aa XFAIL it while it is being worked on.
llvm-svn: 78275
2009-08-06 02:19:20 +00:00
Bob Wilson
6fb1102b9a Add tests for new NEON vld instructions.
llvm-svn: 78264
2009-08-06 00:38:31 +00:00
Bob Wilson
a12289f373 Convert more Neon tests to FileCheck.
llvm-svn: 78261
2009-08-05 23:51:20 +00:00
Anton Korobeynikov
07ce0611d9 Missed pieces for ARM HardFP ABI.
Patch by Sandeep Patel!

llvm-svn: 78225
2009-08-05 19:04:42 +00:00
Dan Gohman
ac47a4b9ed Enable the new no-SP register classes by default. This is to address
PR4572. A few tests have some minor code regressions due to different
coalescing.

llvm-svn: 78217
2009-08-05 17:40:24 +00:00
Anton Korobeynikov
fceaadd678 Add testcases for reg-mem arithemtics added recently
llvm-svn: 78214
2009-08-05 17:04:32 +00:00
Anton Korobeynikov
81300620cf Convert bswap test to filecheck, add more test entries & convert stuff to filecheck
llvm-svn: 78212
2009-08-05 16:50:53 +00:00
Dan Gohman
dda3c89020 Fix a bug in the PIC16 backend.
llvm-svn: 78211
2009-08-05 16:46:43 +00:00
Dan Gohman
1c75d47e13 Change these tests to use function attributes rather than special llc
command-line options.

llvm-svn: 78204
2009-08-05 16:37:27 +00:00
Chris Lattner
3eba9b1f16 checking in broken testcases is not such a good idea.
llvm-svn: 78201
2009-08-05 16:04:18 +00:00
Sanjiv Gupta
2316b46234 Quite a few tests crashed in llc after 78142. This is just one of them. I hope to add a few more.
llvm-svn: 78198
2009-08-05 15:52:14 +00:00
Evan Cheng
eb8c4db271 Disable stack coloring with register for now. It's not able to set kill markers.
llvm-svn: 78179
2009-08-05 07:26:17 +00:00
Evan Cheng
87e24bb76e Another nasty coalescer bug (is there another kind):
After coalescing reg1027's def and kill are both at the same point:
 %reg1027,0.000000e+00 = [56,814:0)  0@70-(814)

bb5:
60   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68   %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76   t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96   t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>

Do not remove the kill marker on t2LDRi12.

llvm-svn: 78178
2009-08-05 07:05:41 +00:00
Dan Gohman
437fedf899 Revert changes accidentally committed along with r78163.
llvm-svn: 78165
2009-08-05 05:38:13 +00:00
Dan Gohman
1110fb6bbd Teach X86FastISel how to handle CCValAssign::BCvt, which is used for
MMX arguments. This fixes PR4684.

llvm-svn: 78163
2009-08-05 05:33:42 +00:00
Evan Cheng
6fc78f15fe Turn some insert_subreg, extract_subreg, subreg_to_reg into implicit_defs.
llvm-svn: 78151
2009-08-05 03:53:14 +00:00
Evan Cheng
9b8516d864 One more. Transfer kill of the larger register when lowering an EXTRACT_SUBREG.
llvm-svn: 78145
2009-08-05 02:25:11 +00:00
Evan Cheng
d85e73ca64 One more place where subreg lowering forgot to transfer undefness.
llvm-svn: 78144
2009-08-05 01:57:22 +00:00
Dan Gohman
5d566d918b Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142
2009-08-05 01:29:28 +00:00