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5009 Commits

Author SHA1 Message Date
Evan Cheng
ee1a44d5d8 Move some pattern fragments to the right files. 
llvm-svn: 26831
 2006-03-17 19:55:52 +00:00
Chris Lattner
647503bccc Disable x86 fastcc from passing args in registers 
llvm-svn: 26824
 2006-03-17 17:27:47 +00:00
Chris Lattner
a71bc63ced Parameterize the number of integer arguments to pass in registers 
llvm-svn: 26818
 2006-03-17 05:10:20 +00:00
Evan Cheng
1f5cb60f28 Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi. 
llvm-svn: 26817
 2006-03-17 02:36:22 +00:00
Evan Cheng
fc79bdafbe Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g. 
ADD32ri8.

llvm-svn: 26816
 2006-03-17 02:25:01 +00:00
Evan Cheng
d16fa97974 - Nuke 16-bit SBB instructions. We'll never use them. 
- Nuke a bogus comment.

llvm-svn: 26815
 2006-03-17 02:24:04 +00:00
Nate Begeman
42736d46b2 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.

llvm-svn: 26814
 2006-03-17 01:40:33 +00:00
Chris Lattner
87dbd49cbe remove dead variable 
llvm-svn: 26813
 2006-03-16 23:52:08 +00:00
Evan Cheng
33055a8aba A new entry. 
llvm-svn: 26810
 2006-03-16 22:44:22 +00:00
Nate Begeman
63c4456867 Notes on how to kill the eeevil brtwoway, and make ppc branch selector 
more target independant, generate better code, and be less conservative.

llvm-svn: 26809
 2006-03-16 22:37:48 +00:00
Chris Lattner
f2008cb73b Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? 
llvm-svn: 26808
 2006-03-16 22:35:59 +00:00
Chris Lattner
8a756c5171 add a note 
llvm-svn: 26807
 2006-03-16 22:25:55 +00:00
Chris Lattner
57773fdac1 teach the ppc backend how to spill/reload vector regs 
llvm-svn: 26806
 2006-03-16 22:24:02 +00:00
Chris Lattner
661ee5d3c1 add callee saved vector regs 
llvm-svn: 26805
 2006-03-16 22:07:06 +00:00
Evan Cheng
0e1abe6e19 Bug fix: condition inverted. 
llvm-svn: 26804
 2006-03-16 22:02:48 +00:00
Evan Cheng
cad75d9f0c Added a way for TargetLowering to specify what values can be used as the 
scale component of the target addressing mode.

llvm-svn: 26802
 2006-03-16 21:47:42 +00:00
Chris Lattner
7f5361757b in functions that use a lot of callee saved regs, this can be more than 
5 instructions away.

llvm-svn: 26801
 2006-03-16 21:31:45 +00:00
Chris Lattner
bf153651b1 Add support for copying registers. still needed: spilling and reloading them 
llvm-svn: 26800
 2006-03-16 20:03:58 +00:00
Chris Lattner
eac8e98036 set TransformToType correctly for vector types. 
llvm-svn: 26797
 2006-03-16 19:50:01 +00:00
Nate Begeman
cbca1b3d14 Another case we could do better on. 
llvm-svn: 26795
 2006-03-16 18:50:44 +00:00
Chris Lattner
b5d0896994 Save/restore VRSAVE once per function, not once per block. 
llvm-svn: 26793
 2006-03-16 18:25:23 +00:00
Chris Lattner
4fd1599ab1 add support for the bitconvert node 
llvm-svn: 26789
 2006-03-16 01:29:53 +00:00
Nate Begeman
e371cb595a Update scheduling info for vrsave instruction 
llvm-svn: 26776
 2006-03-15 05:25:05 +00:00
Chris Lattner
9df7eb4071 add a note 
llvm-svn: 26762
 2006-03-14 19:31:24 +00:00
Chris Lattner
392087f5bd Fix an off by one error that caused PPC LLC failures last night. 
llvm-svn: 26758
 2006-03-14 17:56:49 +00:00
Chris Lattner
80c5fabe4e transformation implemented 
llvm-svn: 26754
 2006-03-14 06:57:34 +00:00
Evan Cheng
ae7469b2c5 PPC LSR pass should use target lowering hooks. 
llvm-svn: 26743
 2006-03-13 23:56:51 +00:00
Evan Cheng
7ec94f2ff7 Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
llvm-svn: 26742
 2006-03-13 23:20:37 +00:00
Evan Cheng
99e87e9147 Update 
llvm-svn: 26741
 2006-03-13 23:19:10 +00:00
Evan Cheng
ed013bd937 Add LSR hooks. 
llvm-svn: 26740
 2006-03-13 23:18:16 +00:00
Chris Lattner
d5ecfd83f1 Handle builtins that directly correspond to GCC builtins. 
llvm-svn: 26737
 2006-03-13 23:09:05 +00:00
Chris Lattner
d0505331d2 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733
 2006-03-13 21:52:10 +00:00
Jim Laskey
c741139c24 Handle the removal of the debug chain. 
llvm-svn: 26729
 2006-03-13 13:07:37 +00:00
Chris Lattner
ea1453c3dc remove two implemented items 
llvm-svn: 26728
 2006-03-13 06:52:22 +00:00
Chris Lattner
1782f3971d I can't convince myself that this is safe, remove the recursive call. 
llvm-svn: 26725
 2006-03-13 06:42:16 +00:00
Chris Lattner
3aff8e6acf Fix a couple of bugs that broke the alpha tester build 
llvm-svn: 26722
 2006-03-13 05:23:59 +00:00
Chris Lattner
9898674f99 Handle cracked instructions in dispatch group formation. 
llvm-svn: 26721
 2006-03-13 05:20:04 +00:00
Chris Lattner
ba10d4e4ab Mark instructions that are cracked by the PPC970 decoder as such. 
llvm-svn: 26720
 2006-03-13 05:15:10 +00:00
Chris Lattner
a278639f29 Several big changes: 
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719
 2006-03-12 09:13:49 +00:00
Chris Lattner
19b93158c1 blr is a branch too 
llvm-svn: 26710
 2006-03-11 21:49:49 +00:00
Chris Lattner
916761949b add an example 
llvm-svn: 26709
 2006-03-11 20:20:40 +00:00
Chris Lattner
115b1be710 add a note 
llvm-svn: 26708
 2006-03-11 20:17:08 +00:00
Chris Lattner
2370965e55 teach the JIT to encode vector registers 
llvm-svn: 26697
 2006-03-10 20:19:50 +00:00
Evan Cheng
471bd00cb5 Add option -enable-x86-lsr to enable x86 loop strength reduction pass. 
llvm-svn: 26665
 2006-03-09 21:51:28 +00:00
Chris Lattner
c08825d684 add a note 
llvm-svn: 26661
 2006-03-09 20:13:21 +00:00
Andrew Lenharth
bbf38867f2 these are copies too 
llvm-svn: 26653
 2006-03-09 18:18:51 +00:00
Chris Lattner
e93eeb189f remove some now-dead code 
llvm-svn: 26652
 2006-03-09 18:07:49 +00:00
Andrew Lenharth
f124519fc8 fcopysign for mixed mode 
llvm-svn: 26651
 2006-03-09 17:56:33 +00:00
Andrew Lenharth
2d36f9d389 relax fcopysign 
llvm-svn: 26649
 2006-03-09 17:47:22 +00:00
Andrew Lenharth
e08d165146 alpha and llvm have different oppinions on which arg is the sign bit 
llvm-svn: 26647
 2006-03-09 17:41:50 +00:00