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12722 Commits

Author SHA1 Message Date
Wesley Peck
6263e05e6d Add scheduling information for the MBlaze backend. 
llvm-svn: 129311
 2011-04-11 22:31:52 +00:00
Rafael Espindola
a1fb8a36f9 Implement cfi_rel_offset 
llvm-svn: 129306
 2011-04-11 21:49:50 +00:00
Rafael Espindola
873ddd983f Add test for previous commit. 
llvm-svn: 129304
 2011-04-11 21:41:34 +00:00
Johnny Chen
77f484c5df Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled. 
rdar://problem/9266265

llvm-svn: 129298
 2011-04-11 21:14:35 +00:00
Evan Cheng
ea0d287a8a Look pass copies when determining whether hoisting would end up inserting more copies. rdar://9266679 
llvm-svn: 129297
 2011-04-11 21:09:18 +00:00
Johnny Chen
b07cb8fee1 Check invalid register encodings for LdFrm/StFrm ARM instructions and flag them as 
invalid instructions.

llvm-svn: 129286
 2011-04-11 18:34:12 +00:00
Bill Wendling
12f5828e1e Revert r129235 pending a vetting of the EH rewrite. 
--- Reverse-merging r129235 into '.':
D    test/Feature/bb_attrs.ll
U    include/llvm/BasicBlock.h
U    include/llvm/Bitcode/LLVMBitCodes.h
U    lib/VMCore/AsmWriter.cpp
U    lib/VMCore/BasicBlock.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/AsmParser/LLLexer.cpp
U    lib/AsmParser/LLToken.h
U    lib/Bitcode/Reader/BitcodeReader.cpp
U    lib/Bitcode/Writer/BitcodeWriter.cpp

llvm-svn: 129259
 2011-04-10 23:18:04 +00:00
Bill Wendling
62d49461b6 Beginning of the Great Exception Handling Rewrite. 
* Add a "landing pad" attribute to the BasicBlock.
* Modify the bitcode reader and writer to handle said attribute.

Later: The verifier will ensure that the landing pad attribute is used in the
appropriate manner. I.e., not applied to the entry block, and applied only to
basic blocks that are branched to via a `dispatch' instruction.

(This is a work-in-progress.)

llvm-svn: 129235
 2011-04-10 00:04:27 +00:00
Chris Lattner
b9b420d588 fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately, 
InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.

llvm-svn: 129223
 2011-04-09 19:41:05 +00:00
Chris Lattner
dab8e5119b look for the verboten argument slot access in any order, thanks to Frits 
for pointing this out

llvm-svn: 129217
 2011-04-09 17:00:34 +00:00
Benjamin Kramer
6f39531981 Don't store Twine temporaries, it's not safe. 
And don't append the name over and over again in the loop.

llvm-svn: 129210
 2011-04-09 11:26:27 +00:00
Eli Friedman
f0ba0c54ec Add back a couple checks removed by r129128; the fact that an intitializer 
is an array of structures doesn't imply it's a ConstantArray of
ConstantStruct.

llvm-svn: 129207
 2011-04-09 09:11:09 +00:00
Chris Lattner
b1efa0b48d fix PR9523, a crash in looprotate on a non-canonical loop made out of indirectbr. 
llvm-svn: 129203
 2011-04-09 07:25:58 +00:00
Chris Lattner
f7623daa2b Fix a bug where RecursivelyDeleteTriviallyDeadInstructions could 
delete the instruction pointed to by CGP's current instruction
iterator, leading to a crash on the testcase.  This fixes PR9578.

llvm-svn: 129200
 2011-04-09 07:05:44 +00:00
Eli Friedman
d3b1c5df33 PR9604; try to deal with RAUW updates correctly in the AST. I'm not convinced 
it's completely safe to cache the AST across LICM runs even with this fix,
but this fix can't hurt.

llvm-svn: 129198
 2011-04-09 06:55:46 +00:00
Eli Friedman
a5b74c486a Test for r129190. 
llvm-svn: 129197
 2011-04-09 06:39:43 +00:00
Chris Lattner
7cc2bc5cd1 fix two completely broken tests, which were matching due to PR9629. 
llvm-svn: 129195
 2011-04-09 06:34:38 +00:00
Chris Lattner
9fb9788a47 remove a bunch of CHECK lines that aren't checking what 
they thought they were, because alternation was expanding
wrong in {{}}'s.

llvm-svn: 129194
 2011-04-09 06:31:06 +00:00
Chris Lattner
badb8ca63c have dag combine zap "store undef", which can be formed during call lowering 
with undef arguments.

llvm-svn: 129185
 2011-04-09 02:32:02 +00:00
Chris Lattner
de62b962e8 don't test for codegen of 'store undef' 
llvm-svn: 129184
 2011-04-09 02:31:26 +00:00
Devang Patel
7adf6f4b5c Add radar number for future reference. 
llvm-svn: 129172
 2011-04-08 23:52:04 +00:00
Devang Patel
39ac307002 Do not emit DW_AT_upper_bound and DW_AT_lower_bound for unbouded array. 
If lower bound is more then upper bound then consider it is an unbounded array.
An array is unbounded if non-zero lower bound is same as upper bound.
If lower bound and upper bound are zero than array has one element.

llvm-svn: 129156
 2011-04-08 21:55:10 +00:00
Evan Cheng
bc053100af Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
llvm-svn: 129152
 2011-04-08 21:37:21 +00:00
Johnny Chen
e2464aa24a Hanlde the checking of bad regs for SMMLAR properly, instead of asserting. 
PR9650
rdar://problem/9257565

llvm-svn: 129147
 2011-04-08 19:41:22 +00:00
Johnny Chen
5b7854afa5 Sanity check the option operand for DMB/DSB. 
PR9648
rdar://problem/9257634

llvm-svn: 129146
 2011-04-08 19:18:07 +00:00
Johnny Chen
2bb229ed27 MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it. 
Add tests for that.

llvm-svn: 129137
 2011-04-08 17:29:58 +00:00
Johnny Chen
16ed2c18a0 Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117
 2011-04-08 00:29:09 +00:00
Rafael Espindola
c2955605da Update tests 
llvm-svn: 129116
 2011-04-07 23:51:25 +00:00
Devang Patel
47e1db49c9 Do not let debug info interfer with branch folding. 
llvm-svn: 129114
 2011-04-07 23:11:25 +00:00
Johnny Chen
0b8e3b20f7 Add a VEXT test. 
llvm-svn: 129111
 2011-04-07 22:04:01 +00:00
Evan Cheng
9049eb2113 Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
llvm-svn: 129107
 2011-04-07 20:31:12 +00:00
Rafael Espindola
a27969f537 Add support for .skip. 
Patch by Roman Divacky.
Fixes PR9361.

llvm-svn: 129106
 2011-04-07 20:26:23 +00:00
Andrew Trick
36a1759769 Added a check in the preRA scheduler for potential interference on a 
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing

llvm-svn: 129100
 2011-04-07 19:54:57 +00:00
Akira Hatanaka
24e15bbe94 Fix handling of functions with internal linkage. 
llvm-svn: 129099
 2011-04-07 19:51:44 +00:00
Johnny Chen
5d23dd2116 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.

llvm-svn: 129098
 2011-04-07 19:28:58 +00:00
Johnny Chen
7198a60b9a Add sanity checking for invalid register encodings for saturating instructions. 
llvm-svn: 129096
 2011-04-07 19:02:08 +00:00
Johnny Chen
ecc113f223 Add some more comments about checkings of invalid register numbers. 
And two test cases.

llvm-svn: 129090
 2011-04-07 18:33:19 +00:00
Devang Patel
17670a995c While hoisting common code from if/else, hoist debug info intrinsics if they match. 
llvm-svn: 129078
 2011-04-07 17:27:36 +00:00
Tanya Lattner
3deb96fad7 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
llvm-svn: 129074
 2011-04-07 15:24:20 +00:00
Johnny Chen
4c81015af7 Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844

llvm-svn: 129050
 2011-04-07 01:37:34 +00:00
Eli Friedman
b0e846a68c PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoad 
is equivalent to any other relevant value; it isn't true in general.
If it is equivalent, the LoopPromoter will tell the AST the equivalence.
Also, delete the PreheaderLoad if it is unused.

Chris, since you were the last one to make major changes here, can you check
that this is sane?

llvm-svn: 129049
 2011-04-07 01:35:06 +00:00
Johnny Chen
1f028bb23e The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047
 2011-04-07 01:05:52 +00:00
Evan Cheng
859dff2c87 Change -arm-divmod-libcall to a target neutral option. 
llvm-svn: 129045
 2011-04-07 00:58:44 +00:00
Johnny Chen
523f8f38f7 Should also check SMLAD for invalid register values. 
rdar://problem/9246650

llvm-svn: 129042
 2011-04-07 00:50:25 +00:00
Owen Anderson
37b60bdf09 Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB. 
llvm-svn: 129038
 2011-04-06 23:35:59 +00:00
Johnny Chen
81aa7d84be A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^

llvm-svn: 129033
 2011-04-06 22:14:48 +00:00
Johnny Chen
96fd9620c8 A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027
 2011-04-06 20:49:02 +00:00
Johnny Chen
b3130a03a7 Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. 
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.

rdar://problem/9240648

llvm-svn: 129015
 2011-04-06 18:27:46 +00:00
Nadav Rotem
ecc7d9a408 This testcase passed even without the fix. Added the target info to make the 
test fail (without the fix). Thanks Dan.

llvm-svn: 128999
 2011-04-06 11:18:29 +00:00
Johnny Chen
765dec3867 Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. 
Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0.  Otherwise, we should reject the insn as invalid.

rdar://problem/9239347
rdar://problem/9239467

llvm-svn: 128977
 2011-04-06 01:18:32 +00:00