Commit Graph

11877 Commits

Author SHA1 Message Date
Bob Wilson
48f9855607 For Darwin, emit all the text section directives together before the dwarf
section directives.  This causes the assembler to put the text sections at
the beginning of the object file, which helps work around a limitation of the
Darwin ARM relocations.  Radar 7255355.

llvm-svn: 83127
2009-09-30 00:23:42 +00:00
David Goodwin
a282690f82 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
llvm-svn: 83122
2009-09-30 00:10:16 +00:00
Jim Grosbach
278d0d5b3d minor cleanup and add clarifying comment
llvm-svn: 83117
2009-09-29 23:17:20 +00:00
Devang Patel
e5be8e79df Remove std::string uses from DebugInfo interface.
llvm-svn: 83083
2009-09-29 18:40:58 +00:00
Evan Cheng
d2bf81c7af Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
llvm-svn: 83058
2009-09-29 07:07:30 +00:00
Jim Grosbach
9cb82ce219 Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
slot for the register scavenger when compiling Thumb1 functions.

llvm-svn: 83023
2009-09-28 22:08:06 +00:00
Evan Cheng
c15ba1de94 Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block.
llvm-svn: 83008
2009-09-28 20:47:15 +00:00
Jakob Stoklund Olesen
31fcbdefbb Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

llvm-svn: 83006
2009-09-28 20:32:26 +00:00
Bob Wilson
bbcf30c05c Pass the optimization level when constructing the ARM instruction selector.
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988
2009-09-28 14:30:20 +00:00
Evan Cheng
54a1a87862 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982
2009-09-28 09:14:39 +00:00
Anton Korobeynikov
2e54b03741 Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument.
Disable rematting of it for now.

llvm-svn: 82975
2009-09-28 07:26:46 +00:00
Anton Korobeynikov
189ce11684 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.

llvm-svn: 82948
2009-09-27 23:52:58 +00:00
Dan Gohman
cd2dd6b7e6 LBRX no longer has an explicit SrcValueSDNode operand, so the type
operand is now at index 2, rather than 3. This fixes the
"Invalid child # of SDNode!" failures on PowerPC.

llvm-svn: 82942
2009-09-27 23:17:47 +00:00
Tilmann Scheller
a23802520a Use explicit structs instead of std::pair to map callee saved regs to spill slots.
llvm-svn: 82909
2009-09-27 17:58:47 +00:00
Evan Cheng
ffe6da0734 Enable pre-regalloc load / store multiple pass for Thumb2.
llvm-svn: 82893
2009-09-27 09:46:04 +00:00
Evan Cheng
48479d0c8f Really remove this option.
llvm-svn: 82838
2009-09-26 02:49:49 +00:00
Evan Cheng
1088c37212 Remove a couple of unused command line options.
llvm-svn: 82837
2009-09-26 02:45:45 +00:00
Evan Cheng
c4e3168b65 Add comment.
llvm-svn: 82836
2009-09-26 02:43:36 +00:00
Anton Korobeynikov
35078c311e Regenerate
llvm-svn: 82814
2009-09-25 22:53:17 +00:00
Evan Cheng
c0edc5ee28 Code clean up and prepare for Thumb2 support. No functionality changes.
llvm-svn: 82805
2009-09-25 21:44:53 +00:00
Dan Gohman
0ac693a89e Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.

llvm-svn: 82794
2009-09-25 20:36:54 +00:00
Dan Gohman
0c4e55a2f8 Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790
2009-09-25 18:54:59 +00:00
David Goodwin
89f5854ddd Finish scheduling itineraries for NEON.
llvm-svn: 82788
2009-09-25 18:38:29 +00:00
Bob Wilson
c5784025af Add some comments to clarify things that I discovered this week.
llvm-svn: 82773
2009-09-25 16:34:46 +00:00
Bob Wilson
94e29af5ac pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned.  For the older ARM APCS ABI, the stack
alignment is just always 4 bytes.  For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.

After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo.  This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4.  (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.

llvm-svn: 82767
2009-09-25 14:41:49 +00:00
Dan Gohman
b5922580d6 Don't try to use pre-indexed addressing with sthbrx/stwbrx
instructions. This fixes a PowerPC bug exposed by some unrelated
changes I'm working on.

llvm-svn: 82743
2009-09-25 00:57:30 +00:00
Jim Grosbach
3d527ff081 Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.

Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.

For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.

llvm-svn: 82734
2009-09-24 23:52:18 +00:00
Chris Lattner
6f702ad1be unconditionally request MMI
llvm-svn: 82716
2009-09-24 21:45:57 +00:00
David Goodwin
3ac3dcacc7 Make the end-of-itinerary mark explicit. Some cleanup.
llvm-svn: 82709
2009-09-24 20:22:50 +00:00
David Goodwin
1d72b88015 Checkpoint NEON scheduling itineraries.
llvm-svn: 82657
2009-09-23 21:38:08 +00:00
Dan Gohman
69f69162d1 Use getStoreSize() instead of getStoreSizeInBits()/8.
llvm-svn: 82656
2009-09-23 21:07:02 +00:00
Dan Gohman
1256f9265b Rename several variables from EVT to more descriptive names, now that EVT
is also the name of their type, as declarations like "EVT EVT" look
really odd.

llvm-svn: 82654
2009-09-23 21:02:20 +00:00
Bob Wilson
e1bb126cbd Remove BlackfinRegisterInfo::getFrameIndexOffset since it is the same as the
default implementation.  Update comment on the default version, which made it
sound like most targets override it.  Currently only X86 and SystemZ override
this method.

llvm-svn: 82651
2009-09-23 20:57:02 +00:00
Anton Korobeynikov
829a3a18d2 ARM does not support offset folding (yet). Disable it for now.
This fixes PR5031. Unfortunately, there is no small testcase :(

llvm-svn: 82643
2009-09-23 19:04:09 +00:00
Dan Gohman
e7e623cd25 Fix X86's unfoldMemoryOperand to properly handle MachineMemOperands.
llvm-svn: 82597
2009-09-23 01:29:41 +00:00
David Goodwin
0db84be1dc Add Cortex-A8 VFP model.
llvm-svn: 82483
2009-09-21 20:52:17 +00:00
Dan Gohman
7a076e642e Add support for rematerializing FsFLD0SS and FsFLD0SD as constant-pool
loads in order to reduce register pressure.

llvm-svn: 82470
2009-09-21 18:30:38 +00:00
Dan Gohman
5eb4fde3c3 Recognize SSE min and max opportunities in even more cases.
And fix a bug with the behavior of min/max instructions formed from
fcmp uge comparisons.

Also, use FiniteOnlyFPMath() for this code instead of UnsafeFPMath,
as it is more specific.

llvm-svn: 82466
2009-09-21 18:03:22 +00:00
Dan Gohman
cca0e25a9e Fix the offset values for these memoperands. For frame objects, the
PseudoSourceValue already effectively represents the offset from the
frame base, so the actual offset should not be added to it.

llvm-svn: 82465
2009-09-21 17:58:09 +00:00
Chris Lattner
d24ead5c1e add a note
llvm-svn: 82442
2009-09-21 06:04:07 +00:00
Daniel Dunbar
db16b2c6bb Register the MachineModuleInfo for the ARM JIT, and update JITDwarfEmitter to
assert if the setModuleInfo hasn't been called.

llvm-svn: 82441
2009-09-21 05:58:35 +00:00
Chris Lattner
64e3a9984b one case handled, expanded another testcase inline.
llvm-svn: 82427
2009-09-21 02:53:57 +00:00
Reid Kleckner
cb38af30a0 Implement the JIT side of the GDB JIT debugging interface. To enable this
feature, either build the JIT in debug mode to enable it by default or pass
-jit-emit-debug to lli.

Right now, the only debug information that this communicates to GDB is call
frame information, since it's already being generated to support exceptions in
the JIT.  Eventually, when DWARF generation isn't tied so tightly to AsmPrinter,
it will be easy to push that information to GDB through this interface.

Here's a step-by-step breakdown of how the feature works:

- The JIT generates the machine code and DWARF call frame info
  (.eh_frame/.debug_frame) for a function into memory.
- The JIT copies that info into an in-memory ELF file with a symbol for the
  function.
- The JIT creates a code entry pointing to the ELF buffer and adds it to a
  linked list hanging off of a global descriptor at a special symbol that GDB
  knows about.
- The JIT calls a function marked noinline that GDB knows about and has put an
  internal breakpoint in.
- GDB catches the breakpoint and reads the global descriptor to look for new
  code.
- When sees there is new code, it reads the ELF from the inferior's memory and
  adds it to itself as an object file.
- The JIT continues, and the next time we stop the program, we are able to
  produce a proper backtrace.

Consider running the following program through the JIT:

#include <stdio.h>
void baz(short z) {
  long w = z + 1;
  printf("%d, %x\n", w, *((int*)NULL));  // SEGFAULT here
}
void bar(short y) {
  int z = y + 1;
  baz(z);
}
void foo(char x) {
  short y = x + 1;
  bar(y);
}
int main(int argc, char** argv) {
  char x = 1;
  foo(x);
}

Here is a backtrace before this patch:
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x2aaaabdfbd10 (LWP 25476)]
0x00002aaaabe7d1a8 in ?? ()
(gdb) bt
#0  0x00002aaaabe7d1a8 in ?? ()
#1  0x0000000000000003 in ?? ()
#2  0x0000000000000004 in ?? ()
#3  0x00032aaaabe7cfd0 in ?? ()
#4  0x00002aaaabe7d12c in ?? ()
#5  0x00022aaa00000003 in ?? ()
#6  0x00002aaaabe7d0aa in ?? ()
#7  0x01000002abe7cff0 in ?? ()
#8  0x00002aaaabe7d02c in ?? ()
#9  0x0100000000000001 in ?? ()
#10 0x00000000014388e0 in ?? ()
#11 0x00007fff00000001 in ?? ()
#12 0x0000000000b870a2 in llvm::JIT::runFunction (this=0x1405b70,
F=0x14024e0, ArgValues=@0x7fffffffe050)
   at /home/rnk/llvm-gdb/lib/ExecutionEngine/JIT/JIT.cpp:395
#13 0x0000000000baa4c5 in llvm::ExecutionEngine::runFunctionAsMain
(this=0x1405b70, Fn=0x14024e0, argv=@0x13f06f8, envp=0x7fffffffe3b0)
   at /home/rnk/llvm-gdb/lib/ExecutionEngine/ExecutionEngine.cpp:377
#14 0x00000000007ebd52 in main (argc=2, argv=0x7fffffffe398,
envp=0x7fffffffe3b0) at /home/rnk/llvm-gdb/tools/lli/lli.cpp:208

And a backtrace after this patch:
Program received signal SIGSEGV, Segmentation fault.
0x00002aaaabe7d1a8 in baz ()
(gdb) bt
#0  0x00002aaaabe7d1a8 in baz ()
#1  0x00002aaaabe7d12c in bar ()
#2  0x00002aaaabe7d0aa in foo ()
#3  0x00002aaaabe7d02c in main ()
#4  0x0000000000b870a2 in llvm::JIT::runFunction (this=0x1405b70,
F=0x14024e0, ArgValues=...)
   at /home/rnk/llvm-gdb/lib/ExecutionEngine/JIT/JIT.cpp:395
#5  0x0000000000baa4c5 in llvm::ExecutionEngine::runFunctionAsMain
(this=0x1405b70, Fn=0x14024e0, argv=..., envp=0x7fffffffe3c0)
   at /home/rnk/llvm-gdb/lib/ExecutionEngine/ExecutionEngine.cpp:377
#6  0x00000000007ebd52 in main (argc=2, argv=0x7fffffffe3a8,
envp=0x7fffffffe3c0) at /home/rnk/llvm-gdb/tools/lli/lli.cpp:208

llvm-svn: 82418
2009-09-20 23:52:43 +00:00
Chris Lattner
5963cbb9c9 update an entry, delete an entry which has been fixed.
llvm-svn: 82398
2009-09-20 17:37:38 +00:00
Bill Wendling
69ad4a0004 --- Reverse-merging r82282 into '.':
U    lib/CodeGen/AsmPrinter/DwarfException.cpp
U    lib/CodeGen/AsmPrinter/DwarfException.h

--- Reverse-merging r82274 into '.':
U    lib/Target/TargetLoweringObjectFile.cpp
G    lib/CodeGen/AsmPrinter/DwarfException.cpp

These revisions were breaking everything.

llvm-svn: 82396
2009-09-20 09:13:15 +00:00
Chris Lattner
3cd0d66e5f remove a temporary hack.
llvm-svn: 82395
2009-09-20 07:47:59 +00:00
Chris Lattner
64f72086ad rename X86ATTAsmPrinter.cpp -> X86AsmPrinter.cpp likewise the .h file.
llvm-svn: 82394
2009-09-20 07:41:30 +00:00
Chris Lattner
9f43a427c6 move target registry stuff to X86ATTAsmPrinter.cpp
llvm-svn: 82393
2009-09-20 07:39:06 +00:00
Chris Lattner
a07073da96 simplify this now that createX86CodePrinterPass is trivial
llvm-svn: 82392
2009-09-20 07:37:51 +00:00
Chris Lattner
271256b7a8 rename X86ATTAsmPrinter class -> X86AsmPrinter
llvm-svn: 82391
2009-09-20 07:35:34 +00:00