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48401 Commits

Author SHA1 Message Date
Bill Wendling
4958d250c9 Remove unused function. 
llvm-svn: 135635
 2011-07-20 23:07:42 +00:00
Bill Wendling
55eb4a26d9 Remove the now defunct getCompactUnwindEncoding method from the frame lowering code. 
llvm-svn: 135634
 2011-07-20 23:04:09 +00:00
Devang Patel
bf27de8340 Refactor. 
llvm-svn: 135633
 2011-07-20 23:00:27 +00:00
Devang Patel
284b502be9 There are two ways to map a variable to its lexical scope. Lexical scope information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode. 
llvm-svn: 135629
 2011-07-20 22:18:50 +00:00
Eli Friedman
c18314afef Clean up includes of llvm/Analysis/ConstantFolding.h so it's included where it's used and not included where it isn't. 
llvm-svn: 135628
 2011-07-20 21:57:23 +00:00
Devang Patel
9914fe1aca While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value. 
llvm-svn: 135627
 2011-07-20 21:57:04 +00:00
Jim Grosbach
572868e146 ARM PKH shift ammount operand printing tweaks. 
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.

llvm-svn: 135626
 2011-07-20 21:40:26 +00:00
Eli Friedman
f98434b2c7 Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef. 
llvm-svn: 135625
 2011-07-20 21:37:47 +00:00
Jim Grosbach
fbaaa3ae98 Tidy up a bit. 
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.

llvm-svn: 135617
 2011-07-20 20:49:03 +00:00
Jim Grosbach
94a88152c9 ARM: Tidy up representation of PKH instruction. 
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.

llvm-svn: 135616
 2011-07-20 20:32:09 +00:00
Benjamin Kramer
575cdb54f1 Fix cmake again :) 
llvm-svn: 135613
 2011-07-20 20:00:06 +00:00
Evan Cheng
c9bc5a9011 Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. 
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.

llvm-svn: 135611
 2011-07-20 19:50:42 +00:00
Eli Friedman
7776a468cf Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. 
llvm-svn: 135607
 2011-07-20 19:36:11 +00:00
Jim Grosbach
1514063b5f ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596
 2011-07-20 18:20:31 +00:00
Eli Friedman
3af0eb7b5f PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS. 
llvm-svn: 135595
 2011-07-20 18:14:33 +00:00
Benjamin Kramer
7636a9969a Initialize the EHFrameSection pointer to zero. 
This should fix the spurious buildbot errors.

llvm-svn: 135594
 2011-07-20 18:13:23 +00:00
Jay Foad
03130446b5 Fix a GCC warning. 
llvm-svn: 135581
 2011-07-20 08:15:21 +00:00
Evan Cheng
55d7fcc5f7 - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
 2011-07-20 07:51:56 +00:00
Evan Cheng
abb07a0c9d Include MCRegisterInfo to eliminate a compilation warning. 
llvm-svn: 135575
 2011-07-20 06:54:19 +00:00
Francois Pichet
74e35bf8ec Fix the CMake build. 
llvm-svn: 135573
 2011-07-20 06:35:24 +00:00
Evan Cheng
380dc98371 Add MCObjectFileInfo and sink the MCSections initialization code from 
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569
 2011-07-20 05:58:47 +00:00
Andrew Trick
57280c0f11 indvars: Added getInsertPointForUses to find a valid place to truncate the IV. 
llvm-svn: 135568
 2011-07-20 05:32:06 +00:00
Andrew Trick
9c4333db13 indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-use 
info. Holding Use* pointers is bad form even though it happened to
work in this case.

llvm-svn: 135566
 2011-07-20 04:39:24 +00:00
NAKAMURA Takumi
19d48c106d X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin. 
llvm-svn: 135564
 2011-07-20 04:02:20 +00:00
Eric Christopher
51af0c896c Extra semi-colon. 
llvm-svn: 135561
 2011-07-20 02:44:39 +00:00
Andrew Trick
ee2d72e5f1 indvars -disable-iv-rewrite fix: derived GEP IVs 
llvm-svn: 135558
 2011-07-20 02:08:58 +00:00
Benjamin Kramer
679af0868f Don't leak CodeGenInfos. 
llvm-svn: 135555
 2011-07-20 01:27:58 +00:00
Akira Hatanaka
a9cbfe8f88 Change name of class. 
llvm-svn: 135550
 2011-07-20 00:53:09 +00:00
Akira Hatanaka
f61c905927 Define classes for definitions of atomic instructions. 
llvm-svn: 135546
 2011-07-20 00:23:01 +00:00
Akira Hatanaka
a50bbdfe15 Lower memory barriers to sync instructions. 
llvm-svn: 135537
 2011-07-19 23:30:50 +00:00
Evan Cheng
9a80b0a7e6 Fix an obvious typo that's preventing x86 (32-bit) from using .literal16. 
llvm-svn: 135535
 2011-07-19 23:14:32 +00:00
Eli Friedman
f809f44cf5 PR10386: Don't try to split an edge from an indirectbr. 
llvm-svn: 135534
 2011-07-19 22:59:41 +00:00
Jim Grosbach
e70c8eb49a Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
 2011-07-19 22:45:10 +00:00
Devang Patel
65afdd27d0 Distinguish between two copies of one inlined variable. 
llvm-svn: 135528
 2011-07-19 22:31:15 +00:00
Jim Grosbach
720b8c6578 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
 2011-07-19 21:59:29 +00:00
Owen Anderson
ad0f17c102 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM. 
llvm-svn: 135524
 2011-07-19 21:06:00 +00:00
Akira Hatanaka
cccc5fca34 Change variable name. 
llvm-svn: 135522
 2011-07-19 20:56:53 +00:00
Jim Grosbach
66af8b4a40 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. 
Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521
 2011-07-19 20:35:35 +00:00
Akira Hatanaka
14e517df43 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520
 2011-07-19 20:34:00 +00:00
Akira Hatanaka
b4db39fa83 Use descriptive variable names. 
llvm-svn: 135514
 2011-07-19 20:11:17 +00:00
Jim Grosbach
9debba28ed ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513
 2011-07-19 20:10:31 +00:00
Jim Grosbach
7e61a1ecf2 Tidy up. 
llvm-svn: 135507
 2011-07-19 19:47:11 +00:00
Jim Grosbach
8ebe7d700a Tighten conditional for 'mov' cc_out. 
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.

llvm-svn: 135506
 2011-07-19 19:45:44 +00:00
Devang Patel
5a4bb57ec5 Reapply r135457. This needs llvm-gcc change, that I forgot to check-in yesterday. 
llvm-svn: 135504
 2011-07-19 19:41:54 +00:00
Jim Grosbach
294b83e3e2 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
 2011-07-19 19:13:28 +00:00
Jim Grosbach
14e26dd644 Remove unused code. 
cc_out and pred operands are added during parsing via custom C++ now.

llvm-svn: 135497
 2011-07-19 18:32:48 +00:00
Akira Hatanaka
19c16a84ff Fix comments. 
llvm-svn: 135496
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
f59cbeec14 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
57d207bc7b Separate code that modifies control flow from code that adds instruction to 
basic blocks.

llvm-svn: 135490
 2011-07-19 17:09:53 +00:00
Jim Grosbach
31cda4ed6d ARM range checking for so_imm operands in assembly parsing. 
llvm-svn: 135489
 2011-07-19 16:50:30 +00:00