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284 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
09012552b8 Add comments. 
llvm-svn: 92883
 2010-01-07 00:51:04 +00:00
Jakob Stoklund Olesen
a63aa4e54b Add Target hook to duplicate machine instructions. 
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

llvm-svn: 92873
 2010-01-06 23:47:07 +00:00
Dan Gohman
5fa04f2707 Delete useless trailing semicolons. 
llvm-svn: 92740
 2010-01-05 17:55:26 +00:00
Nick Lewycky
503ef79cc5 Make this test pass on Linux. 
llvm-svn: 91521
 2009-12-16 07:35:25 +00:00
Anton Korobeynikov
eee906f4f0 Dynamic stack realignment use of sp register as source/dest register 
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

llvm-svn: 90724
 2009-12-06 22:39:50 +00:00
Jim Grosbach
7688d320c9 test case for IV-Users simplification loop improvement 
llvm-svn: 90260
 2009-12-01 21:53:51 +00:00
Evan Cheng
b81878ed80 Enable predication of NEON instructions in Thumb2 mode. 
llvm-svn: 89748
 2009-11-24 08:06:15 +00:00
Jim Grosbach
76b545e988 move fconst[sd] to UAL. <rdar://7414913> 
llvm-svn: 89700
 2009-11-23 21:08:25 +00:00
Jim Grosbach
b7607ee5fe update test for 89694 
llvm-svn: 89695
 2009-11-23 20:39:53 +00:00
Edward O'Callaghan
573a04cfbb Miss two, PR5307. 
llvm-svn: 89596
 2009-11-22 15:35:28 +00:00
Edward O'Callaghan
a295e7bd9b Convert Thumb2 tests to FileCheck for PR5307. 
llvm-svn: 89595
 2009-11-22 15:18:27 +00:00
Jim Grosbach
99c5b49c61 Revert 89562. We're being sneakier than I was giving us credit for, and this 
isn't necessary.

llvm-svn: 89568
 2009-11-21 23:34:09 +00:00
Jim Grosbach
d4603a5c4e Darwin requires a frame pointer for all non-leaf functions to support correct 
backtraces.

llvm-svn: 89562
 2009-11-21 21:40:08 +00:00
Evan Cheng
9828118adf Enable hoisting load from constant memories. 
llvm-svn: 89510
 2009-11-20 23:31:34 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Evan Cheng
5fe8b0b3c5 Also CSE non-pic load from constant pools. 
llvm-svn: 89440
 2009-11-20 02:10:27 +00:00
Evan Cheng
987b8c3d9a More consistent thumb1 asm printing. 
llvm-svn: 89328
 2009-11-19 06:57:41 +00:00
Evan Cheng
c2e359a418 Shrink ldr / str [sp, imm0-1024] to 16-bit instructions. 
llvm-svn: 89326
 2009-11-19 06:32:27 +00:00
Jim Grosbach
d4db2d58ae Enable arm jumpt table adjustment. 
llvm-svn: 89143
 2009-11-17 21:24:11 +00:00
Anton Korobeynikov
6b1a243be8 Forgot to commit test fixes 
llvm-svn: 89138
 2009-11-17 20:38:36 +00:00
Jim Grosbach
b123a9cbc0 Convert to FileCheck 
llvm-svn: 89007
 2009-11-17 00:20:26 +00:00
Jim Grosbach
2f09113304 Convert to FileCheck 
llvm-svn: 89002
 2009-11-17 00:03:38 +00:00
Jim Grosbach
299e4e76c4 Cleanup. Missed removing these when converting. Oops. 
llvm-svn: 89001
 2009-11-17 00:00:33 +00:00
Jim Grosbach
95cf7fad36 Convert to FileCheck 
llvm-svn: 88991
 2009-11-16 23:19:29 +00:00
Jim Grosbach
f4abb1280a Convert to FileCheck 
llvm-svn: 88947
 2009-11-16 20:04:15 +00:00
Jim Grosbach
deee4fbd5d Convert to FileCheck 
llvm-svn: 88942
 2009-11-16 19:46:46 +00:00
Jim Grosbach
0ba7bb08d7 tbb opt off by default 
llvm-svn: 88921
 2009-11-16 17:24:45 +00:00
Jim Grosbach
1aa571da3c Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874
 2009-11-15 21:45:34 +00:00
Jim Grosbach
6028068e88 remove xfail 
llvm-svn: 88817
 2009-11-14 21:57:35 +00:00
Evan Cheng
e43198c166 When expanding t2STRDi8 r, r to two stores, add kill markers correctly. 
llvm-svn: 88734
 2009-11-14 01:50:00 +00:00
Jim Grosbach
8ffdb5d109 Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input. 
llvm-svn: 86997
 2009-11-12 17:19:09 +00:00
Benjamin Kramer
86592507dc Fix typo in run line. 
llvm-svn: 86984
 2009-11-12 12:35:27 +00:00
Evan Cheng
deacae0dd9 RegScavenger::enterBasicBlock should always reset register state. 
llvm-svn: 86972
 2009-11-12 07:49:10 +00:00
Evan Cheng
b0a193db31 - Teach LSR to avoid changing cmp iv stride if it will create an immediate that 
cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
  later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
  users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
  iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.

llvm-svn: 86969
 2009-11-12 07:35:05 +00:00
Dan Gohman
9f47de10e3 Add support for tail duplication to BranchFolding, and extend 
tail merging support to handle more cases.
 - Recognize several cases where tail merging is beneficial even when
   the tail size is smaller than the generic threshold.
 - Make use of MachineInstrDesc::isBarrier to help detect
   non-fallthrough blocks.
 - Check for and avoid disrupting fall-through edges in more cases.

llvm-svn: 86871
 2009-11-11 19:48:59 +00:00
Jim Grosbach
9f37156ae5 Update test 
llvm-svn: 86614
 2009-11-09 22:59:01 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Evan Cheng
899d8cb6a0 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. 
llvm-svn: 86330
 2009-11-07 04:04:34 +00:00
Evan Cheng
8eaaffb9da - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical 
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328
 2009-11-07 03:52:02 +00:00
Evan Cheng
6e3e66375a - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
 2009-11-06 23:52:48 +00:00
Bob Wilson
68772d4db2 Fix a broken test. 
llvm-svn: 86298
 2009-11-06 23:06:42 +00:00
Evan Cheng
8b161e8f4f Fix test. 
llvm-svn: 85986
 2009-11-04 00:42:33 +00:00
Evan Cheng
ed22395c61 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Anton Korobeynikov
bce2703f18 Temporary xfail until PR5367 will be resolved 
llvm-svn: 85848
 2009-11-03 00:37:36 +00:00
Evan Cheng
57f7c7c914 Unbreak ARMBaseRegisterInfo::copyRegToReg. 
llvm-svn: 85787
 2009-11-02 04:44:55 +00:00
Evan Cheng
4a0d47f209 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
llvm-svn: 85743
 2009-11-01 21:12:51 +00:00
Evan Cheng
0151329ce5 Fix tests. 
llvm-svn: 85723
 2009-11-01 18:13:29 +00:00
Evan Cheng
de16fff3e8 Use cbz and cbnz instructions. 
llvm-svn: 85698
 2009-10-31 23:46:45 +00:00
Jim Grosbach
5b094f3b36 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

llvm-svn: 85697
 2009-10-31 22:57:36 +00:00
Jim Grosbach
7dfa53d978 Consolidate test files 
llvm-svn: 85696
 2009-10-31 22:20:56 +00:00
Jim Grosbach
acb31ebed1 Change to use FileCheck 
llvm-svn: 85695
 2009-10-31 22:16:14 +00:00
Jim Grosbach
93bcf7b8ce Make tests more explicit about which instructions are expected. 
llvm-svn: 85694
 2009-10-31 22:14:17 +00:00
Jim Grosbach
84e67e8e5c Grammar tweak to comments 
llvm-svn: 85693
 2009-10-31 22:12:44 +00:00
Jim Grosbach
c003ed5615 Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85691
 2009-10-31 22:10:38 +00:00
Benjamin Kramer
2cc5f86d43 Force triple; darwin's ASM syntax differs from linux's. 
llvm-svn: 85676
 2009-10-31 19:54:06 +00:00
Benjamin Kramer
60dac7de40 Add missing colons for FileCheck. 
llvm-svn: 85674
 2009-10-31 19:22:24 +00:00
Evan Cheng
9178904e56 It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming. 
llvm-svn: 85643
 2009-10-31 03:39:36 +00:00
Bob Wilson
aadcaed95f Fix Thumb2 failures by converting them to FileCheck. 
llvm-svn: 85210
 2009-10-27 06:31:02 +00:00
Evan Cheng
a308ae55a5 Add a couple of ARM cross-rc coalescing tests. 
llvm-svn: 85051
 2009-10-25 08:01:41 +00:00
Evan Cheng
1c169777ca Update tests. 
llvm-svn: 85050
 2009-10-25 07:53:48 +00:00
Jim Grosbach
452de96b04 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
 2009-10-21 20:44:34 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Dan Gohman
c74da745a7 Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail. 
llvm-svn: 84727
 2009-10-21 01:44:44 +00:00
David Goodwin
048b80a70a Checkpoint more aggressive anti-dependency breaking for post-ra scheduler. 
llvm-svn: 84658
 2009-10-20 19:54:44 +00:00
Sandeep Patel
c0762ba283 Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng. 
llvm-svn: 84212
 2009-10-15 22:25:32 +00:00
Evan Cheng
d93fbb28ed Fix tests. 
llvm-svn: 83241
 2009-10-02 06:53:57 +00:00
David Goodwin
a4b73e486e Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default. 
llvm-svn: 83218
 2009-10-01 22:19:57 +00:00
Evan Cheng
a335221976 Forgot this test earlier. 
llvm-svn: 83143
 2009-09-30 08:41:27 +00:00
Evan Cheng
54a1a87862 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo 
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982
 2009-09-28 09:14:39 +00:00
Evan Cheng
ffe6da0734 Enable pre-regalloc load / store multiple pass for Thumb2. 
llvm-svn: 82893
 2009-09-27 09:46:04 +00:00
Daniel Dunbar
923dc62615 "Update" tests for -disable-if-conversion removal. I think branch.ll should just 
be removed, but I XFAIL'd it for now.

llvm-svn: 82847
 2009-09-26 05:29:36 +00:00
Dan Gohman
f2c290dfa6 Convert more tests to avoid llvm-as. 
llvm-svn: 81545
 2009-09-11 18:36:27 +00:00
Evan Cheng
91e719a6a1 Cast MO.getImm() to unsigned before comparing with an unsigned limit. 
llvm-svn: 81318
 2009-09-09 06:05:16 +00:00
Dan Gohman
142428ce64 Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Chris Lattner
ded5762e28 update various tests for signedness changes in .s file. 
llvm-svn: 81289
 2009-09-08 23:51:06 +00:00
Chris Lattner
837420e12f adjust for signedness change. I'd appreciate it if an ARM flavored person 
could look at this: the top undefined bits of an immediate shouldn't affect
isel (cmp vs cmp.w)

llvm-svn: 81288
 2009-09-08 23:44:53 +00:00
Chris Lattner
09a6252bb8 merge thumb2-bic2.ll into thumb2-bic.ll and update for signedness changes. 
llvm-svn: 81285
 2009-09-08 23:41:06 +00:00
Evan Cheng
46e40befe7 Run branch folding if if-converter make some transformations. 
llvm-svn: 80994
 2009-09-04 07:47:40 +00:00
Evan Cheng
493eee1fc7 Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed. 
llvm-svn: 80615
 2009-08-31 20:14:07 +00:00
Evan Cheng
d7a07ab112 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. 
llvm-svn: 80404
 2009-08-28 23:18:09 +00:00
Evan Cheng
984f8efcaa Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset. 
llvm-svn: 80191
 2009-08-27 01:23:50 +00:00
Bob Wilson
af26d40dc0 Fix a typo. Somehow I thought this had passed before, but I guess not. 
llvm-svn: 79937
 2009-08-24 21:17:17 +00:00
Bob Wilson
fadb065745 Convert slow test to use FileCheck. 
llvm-svn: 79935
 2009-08-24 20:33:47 +00:00
Dan Gohman
5022dd9cc9 Make tail merging handle blocks with repeated predecessors correctly, and 
remove RemoveDuplicateSuccessor, as it is no longer necessary, and because
it breaks assumptions made in
MachineBasicBlock::isOnlyReachableByFallthrough.

Convert test/CodeGen/X86/omit-label.ll to FileCheck and add a testcase
for PR4732.

test/CodeGen/Thumb2/thumb2-ifcvt2.ll sees a diff with this commit due to
it being bugpoint-reduced to the point where it doesn't matter what the
condition for the branch is.

Add some more interesting code to
test/CodeGen/X86/2009-08-06-branchfolder-crash.ll, which is the testcase
that originally motivated the RemoveDuplicateSuccessor code, to help
verify that the original problem isn't being re-broken.

llvm-svn: 79338
 2009-08-18 15:18:18 +00:00
Evan Cheng
d4d2a3d0a6 Fix revsh pattern. 
llvm-svn: 79318
 2009-08-18 05:43:23 +00:00
Evan Cheng
b9c8d65369 Fix tests. 
llvm-svn: 79086
 2009-08-15 08:23:11 +00:00
Evan Cheng
9d351a7246 Turn on if-conversion for thumb2. 
llvm-svn: 79084
 2009-08-15 07:59:10 +00:00
Evan Cheng
4e97ccc132 Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim. 
llvm-svn: 79039
 2009-08-14 20:48:13 +00:00
Evan Cheng
7d8caa143b Also shrink immediate branches; also more assembler workarounds. 
llvm-svn: 79014
 2009-08-14 18:31:44 +00:00
Evan Cheng
45d6a21e21 Shrink ADR and LDR from constantpool late during constantpool island pass. 
llvm-svn: 78970
 2009-08-14 00:32:16 +00:00
Evan Cheng
9302c40108 Remove an Darwin assembler workaround. 
llvm-svn: 78777
 2009-08-12 01:56:42 +00:00
Evan Cheng
65f3e466df Shrink ADDS, ADC, RSB, and SUBS. 
llvm-svn: 78776
 2009-08-12 01:49:45 +00:00
Evan Cheng
a29ee9f509 Shrinkify Thumb2 r = add sp, imm. 
llvm-svn: 78745
 2009-08-11 23:00:31 +00:00
Evan Cheng
783028063e Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Evan Cheng
249f07cf57 Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions. 
llvm-svn: 78659
 2009-08-11 09:37:40 +00:00
Evan Cheng
49aac700f4 Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. 
llvm-svn: 78622
 2009-08-10 23:56:04 +00:00
Evan Cheng
f0bb0f5204 Handle the constantfp created during post-legalization dag combiner phase. 
llvm-svn: 78594
 2009-08-10 20:25:59 +00:00
Jakob Stoklund Olesen
f73b30b329 Simplify RegScavenger::forward a bit more. 
Verify that early clobber registers and their aliases are not used.

All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.

The included test case is from PR4686. It has behaviour that was dependent on the order of operands.

llvm-svn: 78465
 2009-08-08 13:18:47 +00:00
Evan Cheng
2bdb247c12 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia. 
llvm-svn: 78410
 2009-08-07 21:19:10 +00:00
Evan Cheng
0dab4cc8a0 Fix support to use NEON for single precision fp math. 
llvm-svn: 78397
 2009-08-07 19:30:41 +00:00
Evan Cheng
a565450757 Another coalescer bug. When a dead copy is eliminated, transfer the kill to a def of the exact register rather than a super-register. 
llvm-svn: 78376
 2009-08-07 07:14:14 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
Evan Cheng
eb8c4db271 Disable stack coloring with register for now. It's not able to set kill markers. 
llvm-svn: 78179
 2009-08-05 07:26:17 +00:00
Evan Cheng
87e24bb76e Another nasty coalescer bug (is there another kind): 
After coalescing reg1027's def and kill are both at the same point:
 %reg1027,0.000000e+00 = [56,814:0)  0@70-(814)

bb5:
60   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68   %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76   t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84   %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96   t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>

Do not remove the kill marker on t2LDRi12.

llvm-svn: 78178
 2009-08-05 07:05:41 +00:00
Evan Cheng
9b8516d864 One more. Transfer kill of the larger register when lowering an EXTRACT_SUBREG. 
llvm-svn: 78145
 2009-08-05 02:25:11 +00:00
Evan Cheng
d85e73ca64 One more place where subreg lowering forgot to transfer undefness. 
llvm-svn: 78144
 2009-08-05 01:57:22 +00:00
Evan Cheng
3020badc5c If the insert_subreg source is <undef>, insert an implicit_def instead of a copy. 
llvm-svn: 78141
 2009-08-05 01:29:24 +00:00
Evan Cheng
e366789b50 Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
llvm-svn: 78126
 2009-08-04 23:47:55 +00:00
Evan Cheng
7963a20a2d Fix test. 
llvm-svn: 78113
 2009-08-04 22:22:58 +00:00
Evan Cheng
2ec9ab08d8 Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet. 
llvm-svn: 78104
 2009-08-04 21:12:13 +00:00
Evan Cheng
29fe8806d5 In thumb mode, r7 is used as frame register. This fixes pr4681. 
llvm-svn: 78086
 2009-08-04 18:46:17 +00:00
Evan Cheng
817618d570 Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. 
llvm-svn: 78030
 2009-08-04 01:41:15 +00:00
Evan Cheng
ff81990e49 Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. 
llvm-svn: 77967
 2009-08-03 08:41:59 +00:00
Evan Cheng
27ee95d344 Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well. 
llvm-svn: 77939
 2009-08-03 02:38:06 +00:00
Evan Cheng
3c2d9a0698 Test both darwin and linux. 
llvm-svn: 77852
 2009-08-02 02:54:34 +00:00
Eli Friedman
cd4d9ff7fa Hack to make this test work on platforms which aren't Macs. Fixing this 
myself because I'm getting tired of seeing the red buildbots, which have 
been red since 5:30PM PDT last night.

Proposed supplement to developer policy: committers should make sure to 
be around to watch for buildbot failures after committing.

llvm-svn: 77785
 2009-08-01 16:37:18 +00:00
Evan Cheng
b9b4b9aa15 Workaround a couple of Darwin assembler bugs. 
llvm-svn: 77781
 2009-08-01 06:13:52 +00:00
Evan Cheng
c165700a7f Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
llvm-svn: 77764
 2009-08-01 01:43:45 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
Evan Cheng
0c9705feed Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.

llvm-svn: 77705
 2009-07-31 18:35:56 +00:00
Evan Cheng
c9f31ae969 When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
llvm-svn: 77642
 2009-07-30 23:29:25 +00:00
David Goodwin
62efc71b9f Darwin assembler now recognizes "orn", so remove workaround. 
llvm-svn: 77627
 2009-07-30 21:51:41 +00:00
David Goodwin
d29f81da16 Darwin assembler now supports "rrx", so remove workaround. 
llvm-svn: 77625
 2009-07-30 21:38:40 +00:00
David Goodwin
2eaffa79af Cleanup and include code selection for some frame index cases. 
llvm-svn: 77622
 2009-07-30 18:56:48 +00:00
Evan Cheng
31ac181755 tbb / tbh instructions only branch forward, not backwards. 
llvm-svn: 77522
 2009-07-29 23:20:20 +00:00
Evan Cheng
fc846dd401 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin
0c9e96bf09 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
David Goodwin
dbc23ece04 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
David Goodwin
e94d490b89 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
David Goodwin
0bcb94eeff ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
David Goodwin
471e9f5b8d Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Evan Cheng
d615e606c4 Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00
Evan Cheng
bddff8fbe0 Remove a duplicated test. 
llvm-svn: 77020
 2009-07-25 00:24:40 +00:00
Evan Cheng
b8b61017e8 Fix these tests. 
llvm-svn: 77006
 2009-07-24 22:42:22 +00:00
Evan Cheng
bbac2397c5 Convert a test to FileCheck. 
llvm-svn: 76954
 2009-07-24 06:01:46 +00:00
Evan Cheng
90f66e1c4e Thumb2 does not allow the use of "pc" register as part of the load / store address. 
llvm-svn: 76909
 2009-07-23 23:09:51 +00:00
Evan Cheng
f6b88eae82 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.

llvm-svn: 76890
 2009-07-23 18:27:47 +00:00
Evan Cheng
192fc19379 Do not select tSXTB / tSXTH in thumb2 mode. 
llvm-svn: 76600
 2009-07-21 18:15:26 +00:00
Evan Cheng
949c2404a2 Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1. 
llvm-svn: 76520
 2009-07-21 00:31:12 +00:00
Anton Korobeynikov
dc39f4fff8 Emit cross regclass register moves for thumb2. 
Minor code duplication cleanup.

llvm-svn: 76124
 2009-07-16 23:26:06 +00:00
David Goodwin
88f38c0380 Fix detection of valid BFC immediates. 
llvm-svn: 75576
 2009-07-14 00:57:56 +00:00
Evan Cheng
20086680b0 Don't put IT instruction before conditional branches. 
llvm-svn: 75361
 2009-07-11 07:26:20 +00:00
Chris Lattner
2bdd9c7807 convert test to use FileCheck, which is much more precise and faster than 
the previous RUN lines.  Hopefully this will be an inspiration for future
tests :)

llvm-svn: 75261
 2009-07-10 18:34:47 +00:00
Evan Cheng
24f2aefc87 Add a thumb2 pass to insert IT blocks. 
llvm-svn: 75218
 2009-07-10 01:54:42 +00:00
David Goodwin
49fbd8d6b7 Use common code for both ARM and Thumb-2 instruction and register info. 
llvm-svn: 75067
 2009-07-08 23:10:31 +00:00
David Goodwin
d19a9aa207 Add rev16 test... xfail for now 
llvm-svn: 75012
 2009-07-08 16:15:06 +00:00
David Goodwin
5bdef4b3f7 Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. 
llvm-svn: 75010
 2009-07-08 16:09:28 +00:00
Evan Cheng
393e38e44b Add Thumb2 movcc instructions. 
llvm-svn: 74946
 2009-07-07 20:39:03 +00:00