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45 Commits

Author SHA1 Message Date
Reid Spencer
4bafa71dc1 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.

llvm-svn: 31380
 2006-11-02 20:25:50 +00:00
Chris Lattner
9cd4e3429e Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.

llvm-svn: 30109
 2006-09-05 02:31:13 +00:00
Jim Laskey
d44e9493e6 Handle callee saved registers in dwarf frame info (lead up to exception 
handling.)

llvm-svn: 29954
 2006-08-29 16:24:26 +00:00
Jim Laskey
c5bcc6d451 Fix some comments. 
llvm-svn: 29880
 2006-08-25 19:40:59 +00:00
Chris Lattner
fd9cbcab4a The PPC64 JIT needs register numbers to encode instructions. 
llvm-svn: 29114
 2006-07-11 20:53:55 +00:00
Chris Lattner
2db97248f8 In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones. 
llvm-svn: 29096
 2006-07-11 00:48:23 +00:00
Chris Lattner
3422f47382 Fix rewriting frame offsets with ixaddr instructions, which implicitly shift 
the offset two bits to the left.

llvm-svn: 28933
 2006-06-27 18:55:49 +00:00
Chris Lattner
75e6449a0f Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file 
llvm-svn: 28889
 2006-06-20 23:18:58 +00:00
Chris Lattner
6f45959365 Gaar! Don't use r11 for CR save/restore, use R0. R11 can be register 
allocated, thus live across the save/reload.  This fixes

llc-beta /MultiSource/Applications/spiff/spiff
llc-beta /MultiSource/Benchmarks/sim/sim:
llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc
llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest:
llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow
llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio
llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode
llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg

and probably others, with -regalloc=local.

llvm-svn: 28761
 2006-06-12 23:59:16 +00:00
Chris Lattner
93ed4373c4 Fix spilling and reloading of CR regs to reload the right values. This fixes 
Olden/power (and probably others) with -regalloc=local.

llvm-svn: 28760
 2006-06-12 21:50:57 +00:00
Evan Cheng
667b133ab9 getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 
llvm-svn: 28378
 2006-05-18 00:12:58 +00:00
Chris Lattner
085cfba0ca Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is 
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.

llvm-svn: 28213
 2006-05-10 06:38:32 +00:00
Chris Lattner
685568510a Move some methods out of MachineInstr into MachineOperand 
llvm-svn: 28102
 2006-05-04 17:52:23 +00:00
Chris Lattner
97f1af2f14 There shalt be only one "immediate" operand type! 
llvm-svn: 28099
 2006-05-04 17:21:20 +00:00
Chris Lattner
20affbd29a Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones). 
Loading and storing off R0 isn't what we wanted.  Also, taking some CR's out of
CRRC seems to cause failures as well.  Further investigation is required.

llvm-svn: 28097
 2006-05-04 16:56:45 +00:00
Nate Begeman
d7b4d2a743 Since we don't handle callee-save CRs right yet, don't allocate them. Also 
don't step on R11 in the middle of a function when saving and restoring CRs

llvm-svn: 28058
 2006-05-02 17:37:31 +00:00
Chris Lattner
fdecddb741 Don't diddle VRSAVE if no registers need to be added/removed from it. This 
allows us to codegen functions as:

_test_rol:
        vspltisw v2, -12
        vrlw v2, v2, v2
        blr

instead of:

_test_rol:
        mfvrsave r2, 256
        mr r3, r2
        mtvrsave r3
        vspltisw v2, -12
        vrlw v2, v2, v2
        mtvrsave r2
        blr

Testcase here: CodeGen/PowerPC/vec_vrsave.ll

llvm-svn: 27777
 2006-04-17 21:48:13 +00:00
Chris Lattner
021f521a41 Vectors that are known live-in and live-out are clearly already marked in 
the vrsave register for the caller.  This allows us to codegen a function as:

_test_rol:
        mfspr r2, 256
        mr r3, r2
        mtspr 256, r3
        vspltisw v2, -12
        vrlw v2, v2, v2
        mtspr 256, r2
        blr

instead of:

_test_rol:
        mfspr r2, 256
        oris r3, r2, 40960
        mtspr 256, r3
        vspltisw v0, -12
        vrlw v2, v0, v0
        mtspr 256, r2
        blr

llvm-svn: 27772
 2006-04-17 21:22:06 +00:00
Chris Lattner
6b76deffb5 Move some knowledge about registers out of the code emitter into the register info. 
llvm-svn: 27770
 2006-04-17 21:07:20 +00:00
Chris Lattner
face261a94 Use a small table instead of macros to do this conversion. 
llvm-svn: 27769
 2006-04-17 20:59:25 +00:00
Nate Begeman
ccd6ea1913 Fix SingleSource/UnitTests/Vector/sumarray-dbl 
llvm-svn: 27594
 2006-04-11 19:44:43 +00:00
Nate Begeman
786d44f822 Fix PR727, correctly handling large stack aligments on ppc 
llvm-svn: 27593
 2006-04-11 19:29:21 +00:00
Jim Laskey
1e0cbe4158 Suppress debug label when not debug. 
llvm-svn: 27588
 2006-04-11 08:11:53 +00:00
Jim Laskey
b93bc75add Foundation for call frame information. 
llvm-svn: 27491
 2006-04-07 16:34:46 +00:00
Chris Lattner
eb9684f6a4 Force use of a frame-pointer if there is anything on the stack that is aligned 
more than the OS keeps the stack aligned.

llvm-svn: 27381
 2006-04-03 22:03:29 +00:00
Jim Laskey
eb38a3e83a Expose base register for DwarfWriter. Refactor code accordingly. 
llvm-svn: 27225
 2006-03-28 13:48:33 +00:00
Jim Laskey
8688957c53 Translate llvm target registers to dwarf register numbers properly. 
llvm-svn: 27180
 2006-03-27 20:18:45 +00:00
Jim Laskey
cec9c18c62 Add support to locate local variables in frames (early version.) 
llvm-svn: 26994
 2006-03-23 18:12:57 +00:00
Chris Lattner
f84f3bf95b When possible, custom lower 32-bit SINT_TO_FP to this: 
_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

llvm-svn: 26943
 2006-03-22 05:30:33 +00:00
Chris Lattner
87dbd49cbe remove dead variable 
llvm-svn: 26813
 2006-03-16 23:52:08 +00:00
Chris Lattner
57773fdac1 teach the ppc backend how to spill/reload vector regs 
llvm-svn: 26806
 2006-03-16 22:24:02 +00:00
Chris Lattner
7f5361757b in functions that use a lot of callee saved regs, this can be more than 
5 instructions away.

llvm-svn: 26801
 2006-03-16 21:31:45 +00:00
Chris Lattner
bf153651b1 Add support for copying registers. still needed: spilling and reloading them 
llvm-svn: 26800
 2006-03-16 20:03:58 +00:00
Chris Lattner
d0505331d2 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733
 2006-03-13 21:52:10 +00:00
Chris Lattner
15cb732cd7 Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) 
llvm-svn: 25913
 2006-02-02 20:12:32 +00:00
Chris Lattner
c8527856c1 Fix an off-by-one error that Nate's eagle eyes caught 
llvm-svn: 25231
 2006-01-11 23:16:29 +00:00
Chris Lattner
5633c9bccf Use the auto-insert BuildMI constructor to avoid an explicit insert. No 
functionality change, just code cleanup.

llvm-svn: 25230
 2006-01-11 23:07:57 +00:00
Chris Lattner
2c8238e494 If a function has a non-zero sized frame, use an add to adjust the stack 
pointer in the epilog, not a load.

llvm-svn: 25229
 2006-01-11 23:03:54 +00:00
Evan Cheng
e720cfd690 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace 
hasInFlag, hasOutFlag.

llvm-svn: 25155
 2006-01-09 18:28:21 +00:00
Evan Cheng
d87688fe72 * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
 2005-12-23 22:14:32 +00:00
Nate Begeman
aecebc076b Add the necessary support to the ISel to allow targets to codegen the new 
alignment information appropriately.  Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack.  Support for
arbitrarily aligned dynamic allocas coming soon.

llvm-svn: 24224
 2005-11-06 09:00:38 +00:00
Chris Lattner
5edea4e9cd Fix the JIT encoding of LWA, LD, STD, and STDU. 
llvm-svn: 23787
 2005-10-18 16:51:22 +00:00
Nate Begeman
b0e319a7c7 First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is 
purely mechanical.

llvm-svn: 23778
 2005-10-18 00:28:58 +00:00
Nate Begeman
723637974b More PPC32 -> PPC changes, as well as merging some classes that were 
redundant after the change.

llvm-svn: 23759
 2005-10-16 05:39:50 +00:00
Chris Lattner
d3946bbea6 Rename PPC32*.h to PPC*.h 
This completes the grand PPC file renaming

llvm-svn: 23745
 2005-10-14 23:59:06 +00:00