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14950 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
20dbe1681b Don't call tablegen'ed Predicate_* functions in the ARM target. 
llvm-svn: 111277
 2010-08-17 20:39:04 +00:00
Jim Grosbach
1d9631950f 80 column cleanup. 
llvm-svn: 111266
 2010-08-17 18:39:16 +00:00
Jakob Stoklund Olesen
74db02758b Don't call Predicate_* methods directly from Sparc target. 
Modernize predicates a bit.

The Predicate_* methods are not used by TableGen any longer. They are only
emitted for the sake of legacy code.

llvm-svn: 111263
 2010-08-17 18:17:12 +00:00
Jim Grosbach
4597437c58 Add hook to examine an instruction referencing a frame index to determine 
whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.

In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.

rdar://8277890

llvm-svn: 111262
 2010-08-17 18:13:53 +00:00
Jim Grosbach
b321adf3af explicitly handle no-op cases for clarity. Fixes clang warning. 
llvm-svn: 111260
 2010-08-17 18:00:41 +00:00
Bob Wilson
e382fce916 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid 
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251
 2010-08-17 17:23:19 +00:00
Chris Lattner
a556264e06 fix emacs language spec's, patch by Edmund Grimley-Evans! 
llvm-svn: 111241
 2010-08-17 16:20:04 +00:00
Bob Wilson
6239dc42c6 Allow more cases of undef shuffle indices and add tests for them. 
llvm-svn: 111226
 2010-08-17 05:54:34 +00:00
Eric Christopher
9a8050c4e1 Copy over some overridden MI wrappers for ARM fast-isel. This is where 
we're adding predicates and optional defs to the MachineInstrs.

llvm-svn: 111222
 2010-08-17 01:25:29 +00:00
Eric Christopher
8a68f2fc40 Make arm fast-isel possible to enable via command line. 
llvm-svn: 111219
 2010-08-17 00:46:57 +00:00
Bob Wilson
1e40f2351c Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937. 
llvm-svn: 111208
 2010-08-16 23:37:17 +00:00
Bob Wilson
d662e8cd02 Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee 
that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196
 2010-08-16 22:26:55 +00:00
Eli Friedman
515b81a494 Comment out some broken/unused/useless instructions which mess up disassembly. 
llvm-svn: 111185
 2010-08-16 21:18:51 +00:00
Eli Friedman
b9707bb261 Don't attempt to SimplifyShortMoveForm in 64-bit mode. 
llvm-svn: 111182
 2010-08-16 21:03:32 +00:00
Matt Fleming
0078681411 Hookup ELF support for X86. 
llvm-svn: 111173
 2010-08-16 18:36:14 +00:00
Bob Wilson
985dab611d Rename sat_shift operand to shift_imm, in preparation for using it for other 
instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168
 2010-08-16 18:27:34 +00:00
Jakob Stoklund Olesen
437fea641b Partially revert r111155. It looks like MSVC is calling an operator<() that 
clang says is unused.

llvm-svn: 111167
 2010-08-16 18:24:54 +00:00
Jakob Stoklund Olesen
a3eb6a36c2 Remove unused functions. 
llvm-svn: 111155
 2010-08-16 17:18:18 +00:00
Bob Wilson
98641e5a51 Remove unused code. 
llvm-svn: 111154
 2010-08-16 17:06:03 +00:00
Argyrios Kyrtzidis
75b69c1de3 Revert r111082. No warnings for this common pattern. 
llvm-svn: 111102
 2010-08-15 10:27:23 +00:00
Eric Christopher
1470fe415c Rework how the non-sse2 memory barrier is lowered so that the 
encoding is correct for the built-in assembler.

Based on a patch from Chris.

llvm-svn: 111083
 2010-08-14 21:51:50 +00:00
Argyrios Kyrtzidis
70b248e3ac Add ATTRIBUTE_UNUSED to methods that are not supposed to be used. 
llvm-svn: 111082
 2010-08-14 21:35:10 +00:00
Chris Lattner
8426971169 improve indentation 
llvm-svn: 111073
 2010-08-14 17:26:09 +00:00
Bob Wilson
b1eb015fc8 T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern. 
llvm-svn: 111068
 2010-08-14 03:18:29 +00:00
Bob Wilson
92bf5a7425 Add a Thumb2 t2RSBrr instruction for disassembly only. 
This fixes another part of PR7792.

llvm-svn: 111057
 2010-08-13 23:24:25 +00:00
Bob Wilson
ca672ee828 Temporarily disable tail calls on ARM to work around some linker problems. 
llvm-svn: 111050
 2010-08-13 22:43:33 +00:00
Bob Wilson
0883c6aae3 Move the Thumb2 SSAT and USAT optional shift operator out of the 
instruction opcode.  This fixes part of PR7792.

llvm-svn: 111047
 2010-08-13 21:48:10 +00:00
Bruno Cardoso Lopes
1eaa601d84 Add comments to some pattern fragments in x86 
llvm-svn: 111041
 2010-08-13 20:39:01 +00:00
Bob Wilson
c044a43293 Refactor the code for disassembling Thumb2 saturate instructions along the 
same lines as the change I made for ARM saturate instructions.

llvm-svn: 111029
 2010-08-13 19:04:21 +00:00
Dale Johannesen
3f9c148d0e Revert 110491. While not wrong, it was based on a 
misanalysis and is undesirable.

llvm-svn: 111028
 2010-08-13 18:43:45 +00:00
Bruno Cardoso Lopes
8b07859f3a Fix comment to reflect code, and remove an unused argument 
llvm-svn: 111022
 2010-08-13 17:50:47 +00:00
Bruno Cardoso Lopes
de5f3f5cb6 Improve comment to make explicit why not to touch this could before JIT goes MC 
llvm-svn: 111021
 2010-08-13 17:44:10 +00:00
Eric Christopher
63c83f19a0 Revert last patch and r110954 as I meant to. 
llvm-svn: 111001
 2010-08-13 02:37:50 +00:00
Eric Christopher
e9a4223bc8 Revert r110954 for now, pseudo instructions can't make it through to the JIT. 
llvm-svn: 111000
 2010-08-13 02:30:00 +00:00
Bruno Cardoso Lopes
350d186d69 Some small clean-up: use of pseudo instructions 
llvm-svn: 110954
 2010-08-12 20:55:18 +00:00
Johnny Chen
78345b1dfe Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951
 2010-08-12 20:46:17 +00:00
Evan Cheng
362df591b6 Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637 
llvm-svn: 110947
 2010-08-12 20:30:05 +00:00
Bruno Cardoso Lopes
7cb26cb8be - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. 
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946
 2010-08-12 20:20:53 +00:00
Bruno Cardoso Lopes
99b5298854 Define AVX 128-bit pattern versions of SET0PS/PD. 
llvm-svn: 110937
 2010-08-12 18:20:59 +00:00
Bruno Cardoso Lopes
43a7ba2bbc Fix comment order 
llvm-svn: 110898
 2010-08-12 02:08:52 +00:00
Bruno Cardoso Lopes
bb491bd56c Begin to support some vector operations for AVX 256-bit intructions. The long 
term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897
 2010-08-12 02:06:36 +00:00
Johnny Chen
fef1367b50 The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td 
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894
 2010-08-12 01:40:54 +00:00
Daniel Dunbar
4f45de1b1e MC/X86/AsmParser: Give an explicit error message when we reject an instruction 
because it could have an ambiguous suffix.

llvm-svn: 110890
 2010-08-12 00:55:42 +00:00
Daniel Dunbar
f2b4982344 MC/AsmParser: Push the burdon of emitting diagnostics about unmatched 
instructions onto the target specific parser, which can do a better job.

llvm-svn: 110889
 2010-08-12 00:55:38 +00:00
Daniel Dunbar
0a98bc5619 tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl', 
target specific parsers can adapt the TargetAsmParser to this.

llvm-svn: 110888
 2010-08-12 00:55:32 +00:00
Johnny Chen
9a37d16281 Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.

llvm-svn: 110880
 2010-08-11 23:35:12 +00:00
Bob Wilson
3582107cf8 Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Jakob Stoklund Olesen
5a62f10abc Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk. 
When a register is defined by a partial load:

  %reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234

That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.

This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.

llvm-svn: 110874
 2010-08-11 23:08:22 +00:00
Dan Gohman
54027cf446 Don't use unsigned char for alignments in TargetData. There aren't 
that many of these things, so the memory savings isn't significant,
and there are now situations where there can be alignments greater
than 128.

llvm-svn: 110836
 2010-08-11 18:15:01 +00:00
Dan Gohman
d91d51116b Use ISD::ADD instead of ISD::SUB with a negated constant. This 
avoids trouble if the return type of TD->getPointerSize() is
changed to something which doesn't promote to a signed type,
and is simpler anyway.

Also, use getCopyFromReg instead of getRegister to read a
physical register's value.

llvm-svn: 110835
 2010-08-11 18:14:00 +00:00