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4d63ca106a
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19344 Commits

Author SHA1 Message Date
Eli Friedman
4d63ca106a Remove the old atomic instrinsics. autoupgrade functionality is included with this patch. 
llvm-svn: 141333
 2011-10-06 23:20:49 +00:00
Bill Wendling
82b6f24ee4 Generate the dispatch table for ARM mode. 
llvm-svn: 141327
 2011-10-06 22:53:00 +00:00
Bill Wendling
3c68e1d212 Refactor some of the code that sets up the entry block for SjLj EH. No functionality change. 
llvm-svn: 141323
 2011-10-06 22:18:16 +00:00
Bill Wendling
c8c252a859 Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!) 
Place the immediate to OR into a register so that it works.

llvm-svn: 141319
 2011-10-06 21:51:21 +00:00
Bill Wendling
e79ca82af3 * Set the low bit of the return address when we are in thumb mode. 
* Some code cleanup.

llvm-svn: 141317
 2011-10-06 21:29:56 +00:00
Justin Holewinski
19679dac62 PTX: Implement signed division 
llvm-svn: 141306
 2011-10-06 20:00:33 +00:00
Craig Topper
2614f6f120 Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. 
llvm-svn: 141274
 2011-10-06 06:44:41 +00:00
Peter Collingbourne
253c6a3690 Build system infrastructure for multiple tblgens. 
llvm-svn: 141266
 2011-10-06 01:51:51 +00:00
Bill Wendling
73eb058991 Add the MBBs before inserting the instructions. Doing it afterwards could lead 
to an infinite loop because of the def-use chains.

Also use a frame load instead of store for the LD instruction.

llvm-svn: 141263
 2011-10-06 00:53:33 +00:00
Cameron Zwarich
5fb7c6643e Always merge profitable shifts on A9, not just when they have a single use. 
llvm-svn: 141248
 2011-10-05 23:39:02 +00:00
Cameron Zwarich
cc5f846d58 Remove a check from ARM shifted operand isel helper methods, which were blocking 
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

llvm-svn: 141247
 2011-10-05 23:38:50 +00:00
Bill Wendling
02aa225b72 Get the proper call site numbers for the landing pads. Also remove a magic 
number (18) for the proper addressing mode.

llvm-svn: 141245
 2011-10-05 23:28:57 +00:00
Jakob Stoklund Olesen
17c6570446 Override TRI::getSubClassWithSubReg for X86. 
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode.  In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.

llvm-svn: 141206
 2011-10-05 20:26:33 +00:00
Justin Holewinski
195e8b81e8 PTX: Fixup a case where getRegClassFor() should be used instead of custom code. 
llvm-svn: 141199
 2011-10-05 18:32:25 +00:00
Akira Hatanaka
28e360356f Fix assertion string. 
llvm-svn: 141197
 2011-10-05 18:17:49 +00:00
Akira Hatanaka
9c77dc9579 Make sure candidate for delay slot filler is not a return instruction. 
llvm-svn: 141196
 2011-10-05 18:16:09 +00:00
Akira Hatanaka
eb6b8949ff Add RA to the set of registers that are defined if instruction is a call. 
llvm-svn: 141194
 2011-10-05 18:11:44 +00:00
Owen Anderson
2d1e930b65 Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set. 
llvm-svn: 141190
 2011-10-05 17:16:40 +00:00
Duncan Sands
da96234020 Ensure OpCode is not used uninitialized. 
llvm-svn: 141184
 2011-10-05 15:13:13 +00:00
Duncan Sands
e0d53880e0 Comment out a variable that is only used in commented out code. 
llvm-svn: 141183
 2011-10-05 15:12:44 +00:00
Duncan Sands
443784b0d0 Remove a bunch of unused variables in the PTX backend (warned about by gcc-4.6). 
llvm-svn: 141182
 2011-10-05 15:11:08 +00:00
NAKAMURA Takumi
c4e7d192d1 MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly. 
llvm-svn: 141174
 2011-10-05 10:11:02 +00:00
Cameron Zwarich
1f890576e3 Add braces around something that throws me for a loop. 
llvm-svn: 141173
 2011-10-05 08:59:10 +00:00
Cameron Zwarich
0cb2071d35 There is no point in setting out-parameters for a ComplexPattern function when 
it returns false, at least as far as I could tell by reading the code.

llvm-svn: 141172
 2011-10-05 08:59:05 +00:00
Craig Topper
c211a8e5a6 Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey. 
llvm-svn: 141162
 2011-10-05 03:29:32 +00:00
Akira Hatanaka
e37b7fb90f Insert space. 
llvm-svn: 141158
 2011-10-05 02:22:49 +00:00
Akira Hatanaka
852a9caebd Do not examine variadic or implicit operands if instruction is a return (jr). 
llvm-svn: 141157
 2011-10-05 02:21:58 +00:00
Akira Hatanaka
eb59ca6c4c Clean up function Filler::delayHasHazard. 
llvm-svn: 141156
 2011-10-05 02:18:58 +00:00
Akira Hatanaka
1d80eaba44 Remove function Filler::insertCallUses. 
Record the registers used and defined by a call in Filler::insertDefsUses.

llvm-svn: 141154
 2011-10-05 02:04:17 +00:00
Akira Hatanaka
3707b9fec8 Clean up Filler::findDelayInstr. 
llvm-svn: 141152
 2011-10-05 01:57:46 +00:00
Akira Hatanaka
594683f3d7 Remove function Filler::isDelayFiller. Check if I is the same instruction that 
filled the last delay slot visited.

llvm-svn: 141151
 2011-10-05 01:30:09 +00:00
Akira Hatanaka
6698bae640 Clean up Filler::runOnMachineBasicBlock. Change interface of 
Filler::findDelayInstr.

llvm-svn: 141150
 2011-10-05 01:23:39 +00:00
Akira Hatanaka
716e3bea9c Define a statistic for the number of slots that were filled with useful 
instructions (instructions that are not NOP).

llvm-svn: 141149
 2011-10-05 01:19:13 +00:00
Akira Hatanaka
c073bd7709 Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before 
I->getDesc().hasDelaySlot() does.

llvm-svn: 141148
 2011-10-05 01:15:31 +00:00
Akira Hatanaka
cf11c1bfbe Add comments and move assignment statement. If sawStore is true, sawLoad does 
not have to be set.

llvm-svn: 141147
 2011-10-05 01:09:37 +00:00
Akira Hatanaka
58d3445fd9 Correct description string of enable-mips-delay-filler. 
llvm-svn: 141146
 2011-10-05 01:06:57 +00:00
Bill Wendling
da6fd6f972 Look at the number of entries in the jump table and jump to a 'trap' block if 
the value exceeds that number.

llvm-svn: 141143
 2011-10-05 00:39:32 +00:00
Bill Wendling
db8e0d2dee Checkpoint for SJLJ EH code. 
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.

llvm-svn: 141140
 2011-10-05 00:02:33 +00:00
Owen Anderson
e255773f3d Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
llvm-svn: 141135
 2011-10-04 23:26:17 +00:00
Kevin Enderby
5a09a8db55 Adding back support for printing operands symbolically to ARM's new disassembler 
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129
 2011-10-04 22:44:48 +00:00
Jakob Stoklund Olesen
0d68d7507e Teach PPCInstrInfo to handle sub-classes. 
This has already been done for most other targets.

llvm-svn: 141083
 2011-10-04 15:28:47 +00:00
Nadav Rotem
a2dd9646d8 Set operation actions to legal types only. 
llvm-svn: 141075
 2011-10-04 12:05:35 +00:00
Nadav Rotem
c4ed7cd5f2 Operations should be custom lowered only if their type is legal. 
Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074
 2011-10-04 10:03:32 +00:00
Craig Topper
9d32602cfd Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Jim Grosbach
f38874e79e ARM assembly parsing and encoding for VMOV immediate. 
llvm-svn: 141046
 2011-10-03 23:38:36 +00:00
Jim Grosbach
5723a6f6ea Tidy up. 80 columns. 
llvm-svn: 141043
 2011-10-03 23:03:26 +00:00
Bill Wendling
68ee098b5a Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it. 
llvm-svn: 141042
 2011-10-03 22:44:15 +00:00
Jim Grosbach
c69258c747 ARM parsing/encoding for VCMP/VCMPE. 
llvm-svn: 141038
 2011-10-03 22:30:24 +00:00
Bill Wendling
834bb83a41 Check-pointing the new SjLj EH lowering. 
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.

llvm-svn: 141031
 2011-10-03 21:25:38 +00:00
Akira Hatanaka
76c268271d Add support for 64-bit logical NOR. 
llvm-svn: 141029
 2011-10-03 21:23:18 +00:00