Commit Graph

6 Commits

Author SHA1 Message Date
Alex Bradbury
d2ade6251c [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate
Match the GNU assembler in supporting immediate operands for these 
instructions even when the reg-reg mnemonic is used.

Differential Revision: https://reviews.llvm.org/D50046
Patch by Kito Cheng.

llvm-svn: 339252
2018-08-08 14:45:44 +00:00
Alex Bradbury
d56655b31e [RISCV] AsmParser support for the li pseudo instruction
The implementation follows the MIPS backend and expands the pseudo instruction 
directly during asm parsing. As the result, only real MC instructions are 
emitted to the MCStreamer. The actual expansion to real instructions is 
similar to the expansion performed by the GNU Assembler.

This patch supersedes D41949.

Differential Revision: https://reviews.llvm.org/D46118
Patch by Mario Werner.

llvm-svn: 334203
2018-06-07 15:35:47 +00:00
Alex Bradbury
a50d6c9f48 Revert "[RISCV] implement li pseudo instruction"
Reverts rL330224, while issues with the C extension and missed common
subexpression elimination opportunities are addressed. Neither of these issues
are visible in current RISC-V backend unit tests, which clearly need
expanding.

llvm-svn: 330281
2018-04-18 19:02:31 +00:00
Alex Bradbury
00d29ca310 [RISCV] implement li pseudo instruction
The implementation follows the MIPS backend and expands the
pseudo instruction directly during asm parsing. As the result, only
real MC instructions are emitted to the MCStreamer. Additionally,
PseudoLI instructions are emitted during codegen. The actual
expansion to real instructions is performed during MI to MC lowering
and is similar to the expansion performed by the GNU Assembler.

Differential Revision: https://reviews.llvm.org/D41949
Patch by Mario Werner.

llvm-svn: 330224
2018-04-17 21:56:40 +00:00
Alex Bradbury
af453b57a3 [RISCV] Enable emission of alias instructions by default
This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.

Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context)

Differential Revision: https://reviews.llvm.org/D41225

Patch by Mario Werner.

llvm-svn: 320797
2017-12-15 09:47:01 +00:00
Alex Bradbury
148dfff3f8 [RISCV] Implement assembler pseudo instructions for RV32I and RV64I
Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

Currently, alias emission is disabled by default to keep the patch
minimal. Alias emission by default will be enabled in a subsequent
patch which also updates all affected tests. Note that this patch
should actually break the floating point MC tests. However, the
used FileCheck configuration is not tight enought to detect the
breakage.

Differential Revision: https://reviews.llvm.org/D40902

Patch by Mario Werner.

llvm-svn: 320487
2017-12-12 15:46:15 +00:00