11 Commits

Author SHA1 Message Date
serge-sans-paille
82b6e6053d llvmbuildectomy - replace llvm-build by plain cmake
No longer rely on an external tool to build the llvm component layout.

Instead, leverage the existing `add_llvm_componentlibrary` cmake function and
introduce `add_llvm_component_group` to accurately describe component behavior.

These function store extra properties in the created targets. These properties
are processed once all components are defined to resolve library dependencies
and produce the header expected by llvm-config.

Differential Revision: https://reviews.llvm.org/D90848
2020-11-13 10:35:24 +01:00
Sergei Trofimovich
cd651a50b4 [VE] Fix initializer visibility
Before the change attempt to link libLTO.so against shared
LLVM library failed as:

```
[ 76%] Linking CXX shared library ../../lib/libLTO.so
... /usr/bin/cmake -E cmake_link_script CMakeFiles/LTO.dir/link.txt --verbose=1
c++ -o ...libLTO.so.12git ...ibLLVM-12git.so
ld: CMakeFiles/LTO.dir/lto.cpp.o: in function `llvm::InitializeAllTargetInfos()':
include/llvm/Config/Targets.def:31: undefined reference to `LLVMInitializeVETargetInfo'
```

It happens because on linux llvm build system sets default
symbol visibility to "hidden". The fix is to set visibility
back to "default" for exported APIs with LLVM_EXTERNAL_VISIBILITY.

Bug: https://bugs.llvm.org/show_bug.cgi?id=47847

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89633
2020-10-19 22:54:41 +01:00
Kazushi (Jam) Marukawa
5b2066afb8 [VE] Add vector load/store instructions
Add vector registers and vector load/store instructions.  Add
regression tests for vector load/store instructions too.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D89183
2020-10-15 09:26:55 +09:00
Kazushi (Jam) Marukawa
26169930ef [VE] Support relocation information in MC layer
Summary:
Change VEAsmParser to support identification with relocation information
in assmebler.  Change VEAsmBackend to support relocation information in
MC layer.  Change VEDisassembler and VEMCCodeEmitter to support binary
generation of branch target operands.  Add REFLONG fixup and variant kind
to support new R_VE_REFLONG ELF symbol.  And, add regression test in both
MC and CodeGen to check binary genaration with relocation information.

Differential Revision: https://reviews.llvm.org/D81553
2020-06-15 11:24:53 +02:00
Kazushi (Jam) Marukawa
1ac9e25624 [VE] Support convert instructions in MC layer
Summary:
Add CVTSQ/CVTDQ/CVTQD/CVTQS instructions.  Add regression tests for
them and other convert instructions of asmparser, mccodeemitter, and
disassembler.  In order to add those instructions, support RD operands
in asmparser, mccodeemitter, and disassembler.

Differential Revision: https://reviews.llvm.org/D81536
2020-06-10 12:22:33 +02:00
Kazushi (Jam) Marukawa
3a6b6c93cc [VE] Support host memory access instructions in MC layer
Summary:
Add LHM/SHM instructions.  Add regression tests for them of asmparser,
mccodeemitter, and disassembler.  In order to add those instructions,
add new decode functions to disassembler, and add new print functions
to instprinter.

Differential Revision: https://reviews.llvm.org/D81535
2020-06-10 10:02:14 +02:00
Kazushi (Jam) Marukawa
04475a0f09 [VE] Support rest of load/store instructions in MC layer
Summary:
Add DLD/DLDU/DLDL/PFCH/TS1AM/TS2AM/TS3AM/ATMAM/CAS instructions newly.
Add regression tests for them to asmparser, mccodeemitter, and disassembler.
In order to add those instructions, change asmparser to support UImm0to2 and
UImm1 operands, add new decode functions to disassembler, and add new print
functions to instprinter.

Differential Revision: https://reviews.llvm.org/D81454
2020-06-09 14:21:00 +02:00
Kazushi (Jam) Marukawa
867b3896d5 [VE] Support floating-point arithmetic instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
floating-point arithmetic instructions.  Add FADDQ, FSUBQ, FMULQ, and
FCMPQ instructions and F128 register class too.

Differential Revision: https://reviews.llvm.org/D81386
2020-06-08 15:58:57 +02:00
Kazushi (Jam) Marukawa
10c96ad267 [VE] Support control instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
control instructions.  Add not defined LPM/SPM/LFR/SFR/SMIR/NOP/LCR/
SCR/TSCR/FIDCR control isntructions newly.  Define MISC registers which
SMIR instruction reads and IC register which SIC instruction reads.
Change asmparser to support Zero, UImm3, and UImm6 operands and MISC
registers.  Change instprinter to support MISC registers also.
Change to use auto to receive dyn_cast also.

Differential Revision: https://reviews.llvm.org/D81370
2020-06-08 11:41:57 +02:00
Kazushi (Jam) Marukawa
e9e4753df0 [VE] Support branch instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
branch instructions.  In order to support them, we enhance asmparser
by adding splitting mnemonic mechanism, e.g. "bgt.l.t" into "b", "gt",
and ".l.t", and parsing mechanism for AS style memory addressing.
We also implment encoding and decoding mechanism for branch instructions.

Differential Revision: https://reviews.llvm.org/D81215
2020-06-05 15:44:02 +02:00
Kazushi (Jam) Marukawa
6414d999ea [VE] Support a basic disassembler for Aurora VE target
Summary:
Add a basic disassember and regression tests of LEA/LD/ST
instructions.  This patch also removes DecoderMethod declarations for
branch and call since those are not implemented in this patch.  They
will be added again later.  This patch also corrects DecoderMethod for
LD/ST instructions for one byte or two.

Differential Revision: https://reviews.llvm.org/D80912
2020-06-03 13:48:42 +02:00