Commit Graph

178804 Commits

Author SHA1 Message Date
Richard Trieu
35115b7a82 [PowerPC] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360731
2019-05-15 00:09:58 +00:00
Richard Trieu
37080f887f [NVPTX] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360729
2019-05-14 23:56:18 +00:00
Richard Trieu
b55a7fcdc3 [MSP430] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360728
2019-05-14 23:45:18 +00:00
Richard Trieu
e38db5c42f [Mips] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360727
2019-05-14 23:34:37 +00:00
Richard Trieu
9d093a2a79 [Lanai] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360726
2019-05-14 23:17:18 +00:00
Richard Trieu
c79810532e [Hexagon] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360724
2019-05-14 23:04:55 +00:00
Richard Trieu
d08f77e242 [BPF] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360722
2019-05-14 22:54:06 +00:00
Richard Trieu
b13f5e8747 [AVR] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360721
2019-05-14 22:41:58 +00:00
Philip Reames
7ef5656249 Use an offset from TOS for idempotent rmw locked op lowering
This was the portion split off D58632 so that it could follow the redzone API cleanup. Note that I changed the offset preferred from -8 to -64. The difference should be very minor, but I thought it might help address one concern which had been previously raised.

Differential Revision: https://reviews.llvm.org/D61862

llvm-svn: 360719
2019-05-14 22:32:42 +00:00
Richard Trieu
4121656a8f [ARM] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360718
2019-05-14 22:29:50 +00:00
Richard Trieu
ad51f676a1 [ARC] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360716
2019-05-14 22:06:04 +00:00
Richard Trieu
1aff655290 [AMDGPU] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360713
2019-05-14 21:54:37 +00:00
Richard Trieu
4e494af6c5 [AArch64] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.

llvm-svn: 360709
2019-05-14 21:33:53 +00:00
Leonard Chan
03d98c8a0b [NewPM] Port HWASan and Kernel HWASan
Port hardware assisted address sanitizer to new PM following the same guidelines as msan and tsan.

Changes:
- Separate HWAddressSanitizer into a pass class and a sanitizer class.
- Create new PM wrapper pass for the sanitizer class.
- Use the getOrINsert pattern for some module level initialization declarations.
- Also enable kernel-kwasan in new PM
- Update llvm tests and add clang test.

Differential Revision: https://reviews.llvm.org/D61709

llvm-svn: 360707
2019-05-14 21:17:21 +00:00
Roman Lebedev
811b53ed69 [NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
Unlike instcombine, we currently don't turn and+shift into shift+and.
We probably should, likely unconditionally.

While i'm adding only all-ones (potentially shifted) mask,
this obviously isn't limited to any particular mask pattern:
https://rise4fun.com/Alive/kmX

Related to https://bugs.llvm.org/show_bug.cgi?id=41874

llvm-svn: 360706
2019-05-14 20:17:04 +00:00
Florian Hahn
a477e510bf [LICM] Allow AliasSetMap to contain top-level loops.
When an outer loop gets deleted by a different pass, before LICM visits
it, we cannot clean up its sub-loops in AliasSetMap, because at the
point we receive the deleteAnalysisLoop callback for the outer loop, the loop
object is already invalid and we cannot access its sub-loops any longer.

Reviewers: asbirlea, sanjoy, chandlerc

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D61904

llvm-svn: 360704
2019-05-14 19:41:36 +00:00
Dmitry Preobrazhensky
1c28b19180 [AMDGPU][GFX8][GFX9] Corrected predicate of v_*_co_u32 aliases
Reviewers: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D61905

llvm-svn: 360702
2019-05-14 19:16:24 +00:00
Nikita Popov
15ef715f9b [LVI][CVP] Add support for abs/nabs select pattern flavor
Based on ConstantRange support added in D61084, we can now handle
abs and nabs select pattern flavors in LVI.

Differential Revision: https://reviews.llvm.org/D61794

llvm-svn: 360700
2019-05-14 18:53:47 +00:00
Alina Sbirlea
0963001ca1 [MemorySSA] LoopSimplify preserves MemorySSA only when flag is flipped.
LoopSimplify can preserve MemorySSA after r360270.
But the MemorySSA analysis is retrieved and preserved only when the
EnableMSSALoopDependency is set to true. Use the same conditional to
mark the pass as preserved, otherwise subsequent passes will get an
invalid analysis.
Resolves PR41853.

llvm-svn: 360697
2019-05-14 18:07:18 +00:00
Philip Reames
36cca714df Fix a release mode warning introduced in r360694
llvm-svn: 360696
2019-05-14 17:50:06 +00:00
Philip Reames
eb6ef692fc [IndVars] Extend reasoning about loop invariant exits to non-header blocks
Noticed while glancing through the code for other reasons.  The extension is trivial enough, decided to just do it.

llvm-svn: 360694
2019-05-14 17:20:10 +00:00
Cameron McInally
4072ff2ca7 Support FNeg in SpeculativeExecution pass
Differential Revision: https://reviews.llvm.org/D61910

llvm-svn: 360692
2019-05-14 16:51:18 +00:00
Philip Reames
8903a4ed3b [Test] Autogen a test for ease of later changing
llvm-svn: 360690
2019-05-14 16:37:29 +00:00
Stanislav Mekhanoshin
c1aa25f196 [AMDGPU] Fixed handling of imemdiate i1 literals
This bug was exposed by the rL360395.

Differential Revision: https://reviews.llvm.org/D61812

llvm-svn: 360689
2019-05-14 16:18:00 +00:00
Tim Renouf
61c1469e3b [AMDGPU] Fixed +DumpCode
The +DumpCode attribute is a horrible hack in AMDGPU to embed the
disassembly of the generated code into the elf file. It is used by LLPC
to implement an extension that allows the application to read back the
disassembly of the code. Longer term, we should re-implement that by
using the LLVM disassembler from the Vulkan driver.

Recent LLVM changes broke +DumpCode. With -filetype=asm it crashed, and
with -filetype=obj I think it did not include any instructions, only the
labels. Fixed with this commit: now it has no effect with -filetype=asm,
and works as intended with -filetype=obj.

Differential Revision: https://reviews.llvm.org/D60682

Change-Id: I6436d86fe2ea220d74a643a85e64753747c9366b
llvm-svn: 360688
2019-05-14 16:17:14 +00:00
Javed Absar
6ea5c62c6a [ARM][CMSE] Add cmse intrinsics for TT instructions
Defines intrinsics cmse_TT, cmse_TTT, cmse_TTA, cmse_TTAT.
No tests here as the tests are in patches that uses these.
Reviewed By: Todd Snider, Dave Green
Differential Revision: 	https://reviews.llvm.org/D59888

llvm-svn: 360687
2019-05-14 16:14:24 +00:00
Stanislav Mekhanoshin
2eb410a496 [AMDGPU] gfx1010 Strengthen some SMEM WAR hazard unit tests. NFC.
Tighten conditions on SMEM WAR hazard unit tests to ensure rejection
of workaround insertion where a s_waitcnt is present in dependency
chain. The current workaround code already conforms to these revise
tests.

llvm-svn: 360686
2019-05-14 16:04:03 +00:00
Simon Pilgrim
d50c5632c1 [X86] Disable shouldFoldConstantShiftPairToMask for scalar shifts on AMD targets (PR40758)
D61068 handled vector shifts, this patch does the same for scalars where there are similar number of pipes for shifts as bit ops - this is true almost entirely for AMD targets where the scalar ALUs are well balanced.

This combine avoids AND immediate mask which usually means we reduce encoding size.

Some tests show use of (slow, scaled) LEA instead of SHL in some cases, but thats due to particular shift immediates - shift+mask generate these just as easily.

Differential Revision: https://reviews.llvm.org/D61830

llvm-svn: 360684
2019-05-14 15:21:28 +00:00
Cullen Rhodes
81830575d0 [AArch64][SVE2] Asm: add SQRDMLAH/SQRDMLSH instructions
Summary:
This patch adds support for the indexed and unpredicated vectors forms of the
SQRDMLAH and SQRDMLSH instructions.

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: rovka

Differential Revision: https://reviews.llvm.org/D61515

llvm-svn: 360683
2019-05-14 15:10:16 +00:00
Cullen Rhodes
dc081e21c0 [AArch64][SVE2] Asm: add integer multiply-add/subtract (indexed) instructions
Summary:
This patch adds support for the following instructions:

  MLA mul-add, writing addend (Zda = Zda +  Zn * Zm[idx])
  MLS mul-sub, writing addend (Zda = Zda + -Zn * Zm[idx])

Predicated forms of these instructions were added in SVE.

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: rovka

Differential Revision: https://reviews.llvm.org/D61514

llvm-svn: 360682
2019-05-14 15:01:00 +00:00
Paul Robinson
4d8fc6dc19 Replace lit feature keyword 'not_COFF' with 'uses_COFF'.
Differential Revision: https://reviews.llvm.org/D61791

llvm-svn: 360680
2019-05-14 14:51:54 +00:00
Fangrui Song
2210b8bc74 DWARF v5: emit DW_AT_addr_base if DW_AT_low_pc references .debug_addr
The condition !AddrPool.empty() is tested before attachRangesOrLowHighPC(), which may add an entry to AddrPool. We emit DW_AT_low_pc (DW_FORM_addrx) but may incorrectly omit DW_AT_addr_base for LineTablesOnly. This can be easily reproduced:

clang -gdwarf-5 -gmlt -c a.cc

Fix this by moving !AddrPool.empty() below.

This was discovered while investigating an lld crash (fixed by D61889) on such object files: ld.lld --gdb-index a.o

Reviewed By: probinson

Differential Revision: https://reviews.llvm.org/D61891

llvm-svn: 360678
2019-05-14 14:37:26 +00:00
Lei Huang
74b05fb18e [PowerPC] Custom lower known CR bit spills
For known CRBit spills, CRSET/CRUNSET, it is more efficient to load and spill
the known value instead of extracting the bit.

eg. This sequence is currently used to spill a CRUNSET:
    crclr   4*cr5+lt
    mfocrf  r3,4
    rlwinm  r3,r3,20,0,0
    stw     r3,132(r1)

This patch custom lower it to:
    li  r3,0
    stw r3,132(r1)

Differential Revision: https://reviews.llvm.org/D61754

llvm-svn: 360677
2019-05-14 14:27:06 +00:00
George Rimar
209b337963 [llvm-readobj] - Apply clang format. NFC.
I am a bit tired of the formatting issues.

llvm-svn: 360676
2019-05-14 14:22:44 +00:00
Simon Pilgrim
fcf46753c5 [APFloat] APFloat::Storage::Storage - fix use after move
This was mentioned both in https://www.viva64.com/en/b/0629/ and by scan-build checks

llvm-svn: 360675
2019-05-14 14:13:30 +00:00
Xing Xue
ed2ba72592 [lit][tests]Add feature libcxx-used and use it in llvm-*-fuzzer tests
When a LLVM binary such as llvm-*-fuzzer is built with libc++, it has dependency on libc++. The path to find shared libraries specified in llvm-*-fuzzer is relative. As a result, these binaries cannot be copied to an arbitrary directory and launched from there. Changes in this patch add a LIT feature to indicate that libc++ is used to build and, based on the feature exclude test cases that test by copying llvm-*-fuzzer binaries to a directory.

Reviewers: hubert.reinterpretcast, dberris, amyk, jasonliu, EricWF

Reviewed By: hubert.reinterpretcast, amyk

Subscribers: javed.absar, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61265

llvm-svn: 360672
2019-05-14 13:54:33 +00:00
Kit Barton
3d8187d171 Save the induction binary operator in IVDescriptors for non FP induction variables.
Summary:
Currently InductionBinOps are only saved for FP induction variables, the PR extends it with non FP induction variable, so user of IVDescriptors can query the InductionBinOps for integer induction variables.

The changes in hasUnsafeAlgebra() and getUnsafeAlgebraInst() are required for the existing LIT test cases to pass. As described in the comment of the two functions, one of the requirement to return true is it is a FP induction variable. The checks was not needed because InductionBinOp was not set on non FP cases before.

https://reviews.llvm.org/D60565 depends on the patch.

Committed on behalf of @Whitney (Whitney Tsang).

Reviewers: jdoerfert, kbarton, fhahn, hfinkel, dmgreen, Meinersbur

Reviewed By: jdoerfert

Subscribers: mgorny, hiraditya, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61329

llvm-svn: 360671
2019-05-14 13:26:36 +00:00
Tim Northover
865845db70 TableGen: support #ifndef in addition to #ifdef.
TableGen has a limited preprocessor, which only really supports
easier.

llvm-svn: 360670
2019-05-14 13:04:25 +00:00
Thomas Preud'homme
a6a999ae4c Reinstate "FileCheck [5/12]: Introduce regular numeric variables"
This reinstates r360578 (git e47362c1ec1ea31b626336cc05822035601c3e57),
reverted in r360653 (git 004393681c25e34e921adccc69ae6378090dee54),
with a fix for the list added in FileCheck.rst to build without error.

Copyright:
    - Linaro (changes up to diff 183612 of revision D55940)
    - GraphCore (changes in later versions of revision D55940 and
                 in new revision created off D55940)

Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar,
arichardson, rnk

Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar,
arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60385

llvm-svn: 360665
2019-05-14 11:58:30 +00:00
Simon Pilgrim
4de72d6f1a [X86] X86TargetLowering::LowerINTRINSIC_WO_CHAIN - ensure rounding control is initialized. NFCI.
Fixes scan-build warnings

llvm-svn: 360664
2019-05-14 11:30:39 +00:00
Tim Northover
18a8d29140 AArch64: support binutils-like things on arm64_32.
This adds support for the arm64_32 watchOS ABI to LLVM's low level tools,
teaching them about the specific MachO choices and constants needed to
disassemble things.

llvm-svn: 360663
2019-05-14 11:25:44 +00:00
Tim Northover
79973f8a9d GlobalOpt: do not promote globals used atomically to constants.
Some atomic loads are implemented as cmpxchg (particularly if large or
floating), and that usually requires write access to the memory involved
or it will segfault.

We can still propagate the constant value to users we understand though.

llvm-svn: 360662
2019-05-14 11:03:13 +00:00
James Henderson
25eba33f86 [llvm-objcopy] Cache gnu_debuglink's target CRC
.gnu_debuglink section contains information regarding file with
debugging symbols, identified by its CRC32. This target file is not
intended to ever change or it would invalidate the stored checksum, yet
the checksum is calculated over and over again for each of the objects
inside the archive, usually hundreds of times.

This patch precomputes the CRC32 of the target once and then reuses the
value where required, saving lots of redundant I/O.

The error message reported should stay the same, although now it might
be reported earlier.

Reviewed by: jhenderson, jakehehrlich, MaskRay

Differential Revision: https://reviews.llvm.org/D61343

Patch by Michal Janiszewski

llvm-svn: 360661
2019-05-14 10:59:04 +00:00
James Henderson
8be9356a5a [test]Make test work on Windows
Previously, the test didn't work because '\' characters appeared in the
sed string, causing bogus escape characters to form in the substituted
string literal. Switching to using '%/p' causes the path to be emitted
with '/' characters instead, so that there are are no escaping issues.

Reviewed by: kzhuravl, grimar

Differential Revision: https://reviews.llvm.org/D61856

llvm-svn: 360660
2019-05-14 10:53:35 +00:00
Simon Pilgrim
4b52274230 [MemorySanitizer] getMMXVectorTy - assert valid element size. NFCI.
Fixes scan-build warnings

llvm-svn: 360658
2019-05-14 10:29:18 +00:00
Diana Picus
d9cee1e985 [IRTranslator] Don't hardcode GEP index type
When breaking up loads and stores of aggregates, the IRTranslator uses
LLT::scalar(64) for the index type of the G_GEP instructions that
compute the addresses. This is unnecessarily large for 32-bit targets.
Use the int ptr type provided by the DataLayout instead.

Note that we're already doing the right thing when translating
getelementptr instructions from the IR. This is just an oversight when
generating new ones while translating loads/stores.

Both x86 and AArch64 already have tests confirming that the old
behaviour is preserved for 64-bit targets.

Differential Revision: https://reviews.llvm.org/D61852

llvm-svn: 360656
2019-05-14 09:25:17 +00:00
Thomas Preud'homme
7206726a7e Revert "FileCheck [5/12]: Introduce regular numeric variables"
This reverts r360578 (git e47362c1ec1ea31b626336cc05822035601c3e57) to
solve the sphinx build failure on
http://lab.llvm.org:8011/builders/llvm-sphinx-docs buildbot.

llvm-svn: 360653
2019-05-14 08:43:11 +00:00
Alex Denisov
34de1a1455 Add guidelines/recommendations for organizers of LLVM Socials
Differential Revision: https://reviews.llvm.org/D61550

llvm-svn: 360651
2019-05-14 07:20:58 +00:00
Philip Reames
70f8205375 [X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets
This is a follow on to D58632, with the same logic. Given a memory operation which needs ordering, but doesn't need to modify any particular address, prefer to use a locked stack op over an mfence.

Differential Revision: https://reviews.llvm.org/D61863

llvm-svn: 360649
2019-05-14 04:43:37 +00:00
Fangrui Song
a07a8b5b12 [Object] Change ObjectFile::getSectionContents to return Expected<ArrayRef<uint8_t>>
Change
std::error_code getSectionContents(DataRefImpl, StringRef &) const;
to
Expected<ArrayRef<uint8_t>> getSectionContents(DataRefImpl) const;

Many object formats use ArrayRef<uint8_t> as the underlying type, which
is generally better than StringRef to represent binary data, so change
the type to decrease the number of type conversions.

Reviewed By: ruiu, sbc100

Differential Revision: https://reviews.llvm.org/D61781

llvm-svn: 360648
2019-05-14 04:22:51 +00:00