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805 Commits

Author SHA1 Message Date
Dan Gohman
f223eaafcd Fix a DAGCombiner optimization to respect volatile qualification. 
llvm-svn: 48994
 2008-03-31 20:32:52 +00:00
Dan Gohman
227e702cae Fix a tokenfactor node to use the load chain rather than the 
load value. This fixes PR2177.

llvm-svn: 48932
 2008-03-28 23:45:16 +00:00
Evan Cheng
6cbce6b602 Fix a memory bug: increment an iterator of a deleted machine instr. 
llvm-svn: 48853
 2008-03-27 01:27:25 +00:00
Evan Cheng
6fc37c8f25 One more coalescer fix wrt deadness propagation. 
llvm-svn: 48837
 2008-03-26 20:15:49 +00:00
Evan Cheng
8d222d6221 Avoid commuting a def MI in order to coalesce a copy instruction away if any use of the same val# is a copy instruction that has already been coalesced. 
llvm-svn: 48833
 2008-03-26 19:03:01 +00:00
Dale Johannesen
8c1e95810f Use ## for comment delimiter on darwin x86-32, so 
llvm's output .s files will go through gcc -std=c99
without triggering preprocesser errors.  Approach
suggested by Daveed Vandevoorde.

llvm-svn: 48808
 2008-03-25 23:29:30 +00:00
Evan Cheng
8cb64d8e8b Handle a special case xor undef, undef -> 0. Technically this should be transformed to undef. But this is such a common idiom (misuse) we are going to handle it. 
llvm-svn: 48792
 2008-03-25 20:08:07 +00:00
Dan Gohman
58ad056286 Add CMP32mr and friends to the load-unfolding table. Among 
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.

llvm-svn: 48777
 2008-03-25 16:53:19 +00:00
Tanya Lattner
b6a27ed83f Byebye llvm-upgrade! 
llvm-svn: 48762
 2008-03-25 04:26:08 +00:00
Evan Cheng
7c1dcd8371 lastRegisterUse() should ignore identity copies. Those will be erased. 
llvm-svn: 48759
 2008-03-25 02:02:19 +00:00
Bill Wendling
2097b72649 Use the bit size of the operand instead of the hard-coded 32 to generate the 
mask.

llvm-svn: 48750
 2008-03-24 23:16:37 +00:00
Evan Cheng
dbdf48276a - SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction. 
llvm-svn: 48746
 2008-03-24 21:52:23 +00:00
Dan Gohman
b9c5e6258f APIntify SelectionDAG's EXTRACT_ELEMENT code. 
llvm-svn: 48726
 2008-03-24 16:38:05 +00:00
Bill Wendling
f607f27320 New testcase. 
llvm-svn: 48697
 2008-03-22 22:27:01 +00:00
Evan Cheng
874aee2eec Teach DAG combiner to commute commutable binary nodes in order to achieve sdisel CSE. 
llvm-svn: 48673
 2008-03-22 01:55:50 +00:00
Dan Gohman
59aeac6320 Handle getresult instructions in different basic blocks 
from their aggregate operands by moving the getresult
instructions.

llvm-svn: 48657
 2008-03-21 21:01:32 +00:00
Chris Lattner
8a4fa95cae Add support for calls that return two FP values in 
ST(0)/ST(1).

llvm-svn: 48634
 2008-03-21 06:38:26 +00:00
Chris Lattner
933d0d318b disable a bogus assertion. 
llvm-svn: 48633
 2008-03-21 06:01:05 +00:00
Chris Lattner
260473f983 Enable support for returning two long-double values in ST(0)/ST(1). 
This allows us to compile fp-stack-2results.ll into:

_test:
	fldz
	fld1
	ret

which returns 1 in ST(0) and 0 in ST(1).  This is needed for x86-64
_Complex long double.

llvm-svn: 48632
 2008-03-21 05:57:20 +00:00
Evan Cheng
4ae9fee64c Undo 48570. Correctly match mmx shift instructions with an immediate operand. 
llvm-svn: 48627
 2008-03-21 00:40:09 +00:00
Evan Cheng
8ecb189245 Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m))) 
llvm-svn: 48578
 2008-03-20 02:18:41 +00:00
Scott Michel
e747d20130 Add more patterns to match in the integer comparison test harnesses. 
Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.

llvm-svn: 48575
 2008-03-20 00:51:36 +00:00
Evan Cheng
6f729b2820 Add intrinsics to match mmx shift builtin's with immediate operand. 
llvm-svn: 48569
 2008-03-19 23:38:52 +00:00
Dan Gohman
c9dec33f3f Add support for multiple return values for the PPC target by 
converting call result lowering to use the CallingConvLowering
infastructure.

llvm-svn: 48552
 2008-03-19 21:39:28 +00:00
Christopher Lamb
958b0494c3 Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491. 
llvm-svn: 48542
 2008-03-19 08:30:06 +00:00
Evan Cheng
e9aa507edc Fixed a coalescer bug caused by a typo. 
llvm-svn: 48526
 2008-03-19 02:26:36 +00:00
Evan Cheng
3d9309c11d Fix live variables issues: 
1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue.
2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register:
   = EAX, AX<imp-use,kill>
...
AX =
In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things.

llvm-svn: 48521
 2008-03-19 00:52:20 +00:00
Evan Cheng
5ac87b837e Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it! 
llvm-svn: 48515
 2008-03-18 23:36:35 +00:00
Bill Wendling
c8f3fc7c3d It might be nice to have this run as x86 on non-x86 platforms... 
llvm-svn: 48511
 2008-03-18 22:38:22 +00:00
Bill Wendling
5ea2aec3ac Temporarily revert r48491. It's breaking test/CodeGen/X86/xorl.ll. 
llvm-svn: 48510
 2008-03-18 22:29:51 +00:00
Dale Johannesen
7f51ebc90c Make conversions of i8/i16 to ppcf128 work. 
llvm-svn: 48493
 2008-03-18 17:28:38 +00:00
Christopher Lamb
1d70509b55 Target independent DAG transform to use truncate for field extraction + sign extend on targets where this is profitable. Passes nightly on x86-64. 
llvm-svn: 48491
 2008-03-18 16:46:39 +00:00
Evan Cheng
5750c3cd1e Rewrite code that propagate isDead information after a dead copy is coalesced. This remove some ugly spaghetti code and fixed a number of subtle bugs. 
llvm-svn: 48490
 2008-03-18 08:26:47 +00:00
Chris Lattner
bb335409c2 ensure we continue matching x86-64 rotates. 
llvm-svn: 48437
 2008-03-17 01:35:03 +00:00
Evan Cheng
3612a7ed30 Fix PR2138. Apparently any modification to a std::multimap (including remove entries for a different key) can invalidate multimap iterators. 
llvm-svn: 48371
 2008-03-14 20:44:01 +00:00
Dan Gohman
486f664806 More APInt-ification. 
llvm-svn: 48344
 2008-03-13 22:13:53 +00:00
Evan Cheng
53c3dd0267 New test case. 
llvm-svn: 48338
 2008-03-13 08:05:02 +00:00
Evan Cheng
a76bb6e64e A test case I forgot to check in. 
llvm-svn: 48335
 2008-03-13 06:42:46 +00:00
Evan Cheng
0b8b1647dd TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one. 
llvm-svn: 48333
 2008-03-13 06:37:55 +00:00
Evan Cheng
620fd19798 Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: 
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!

llvm-svn: 48307
 2008-03-12 22:19:41 +00:00
Dan Gohman
2ec41788ab Fix this test on hosts that don't have sse2. 
llvm-svn: 48296
 2008-03-12 20:40:51 +00:00
Dan Gohman
2a124430e9 Make this test x86-specific for now; targets that don't use 
the automated CallingConv code to handle return values typically
don't support multiple return values.

llvm-svn: 48265
 2008-03-12 00:25:14 +00:00
Dan Gohman
155ffdd955 Basic feature test for multiple return values in codegen. 
llvm-svn: 48260
 2008-03-11 23:53:16 +00:00
Anton Korobeynikov
d2fd135594 Testcase for PR2137 
llvm-svn: 48258
 2008-03-11 22:43:42 +00:00
Anton Korobeynikov
efa9405b94 Update testcase for recent aliases change 
llvm-svn: 48250
 2008-03-11 21:42:20 +00:00
Dan Gohman
f9f25bd41b Add a test to ensure that all-ones vectors are materialized with pcmpeqd. 
llvm-svn: 48247
 2008-03-11 21:37:00 +00:00
Dan Gohman
1fece90de9 Use the correct value for InSignBit. 
llvm-svn: 48245
 2008-03-11 21:29:43 +00:00
Chris Lattner
fd2c24af72 Implement basic support for the 'f' register class constraint. This basically 
works, but probably won't if you mix it with 't' or 'u' yet.

llvm-svn: 48243
 2008-03-11 19:50:13 +00:00
Dale Johannesen
c03216ac3e The feature this is testing did not work in the general case, 
and has been removed.

llvm-svn: 48232
 2008-03-11 17:48:26 +00:00
Evan Cheng
6a30fc4e94 Learn how to xfail a test. 
llvm-svn: 48219
 2008-03-11 07:51:31 +00:00