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16995 Commits

Author SHA1 Message Date
Kalle Raiskila
7401b2a1db Split up RotateShift itinerary in SPU. 
'rotq*' and 'shlq*' instructions go to the odd pipeline,
wheras the inter-vector equivalents 'rot*', 'shl*' go 
to the even.

llvm-svn: 123622
 2011-01-17 13:33:19 +00:00
Kalle Raiskila
8eaf0e83d5 Don't crash SPU BE with memory accesses with big alignmnet. 
llvm-svn: 123620
 2011-01-17 11:59:20 +00:00
Evan Cheng
53ec6fc591 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. 
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
 2011-01-17 08:03:18 +00:00
Anton Korobeynikov
2a9d9ef36f Provide instruction sizes for ARMv5 variants of MUL instructions. 
This fixes PR8987

llvm-svn: 123598
 2011-01-16 21:28:33 +00:00
Anders Carlsson
d0103ebf92 Update README.txt to remove the DAE enhancement. 
llvm-svn: 123597
 2011-01-16 21:26:15 +00:00
Rafael Espindola
7933fffe38 Only put unnamed_addr constants in mergeable sections. Fixes PR8297. 
llvm-svn: 123585
 2011-01-16 17:19:34 +00:00
Chris Lattner
dde85de90f fix PR8514, a bug where the "heroic" transformation of shift/and 
into and/shift would cause nodes to move around and a dangling pointer
to happen.  The code tried to avoid this with a HandleSDNode, but 
got the details wrong.

llvm-svn: 123578
 2011-01-16 08:48:11 +00:00
Chris Lattner
91f1b21cf1 add some commentary 
llvm-svn: 123572
 2011-01-16 06:39:44 +00:00
Evan Cheng
144b435a15 Spill R4 if it's going to be used to restore SP from FP. 
llvm-svn: 123567
 2011-01-16 05:14:33 +00:00
Venkatraman Govindaraju
fe346f6cba Implement AnalyzeBranch in Sparc Backend. 
llvm-svn: 123561
 2011-01-16 03:15:11 +00:00
Chris Lattner
24ea7f696e fix PR8981, a crash trying to form a conditional inc with a floating point compare. 
llvm-svn: 123560
 2011-01-16 02:56:53 +00:00
Chris Lattner
c4d1d86d3e reapply my fix for PR8961 with a tweak to properly handle 
multi-instruction sequences like calls.  Many thanks to Jakob for
finding a testcase.

llvm-svn: 123559
 2011-01-16 02:27:38 +00:00
Chandler Carruth
a3261fcca5 Simplify a README.txt entry significantly to expose the core issue. 
llvm-svn: 123556
 2011-01-16 01:40:23 +00:00
Eric Christopher
d675e0b362 80-col. 
llvm-svn: 123505
 2011-01-15 00:25:09 +00:00
Bob Wilson
e6b8ba1ae4 Fix a comment. 
llvm-svn: 123497
 2011-01-15 00:09:18 +00:00
Eric Christopher
b00cef51d8 Fix 80-cols. 
llvm-svn: 123494
 2011-01-14 23:50:53 +00:00
Ted Kremenek
4b09cdedb2 'HiReg' is written but never read. Nuke its 
declaration and its assignments.

Found by clang static analyzer.

llvm-svn: 123486
 2011-01-14 22:34:13 +00:00
Anton Korobeynikov
1f9df99db1 Add a possibility to switch between CFI directives- and table-based frame description emission. Currently all the backends use table-based stuff. 
llvm-svn: 123476
 2011-01-14 21:58:08 +00:00
Anton Korobeynikov
6b2f110a3d Cleanup 
llvm-svn: 123475
 2011-01-14 21:57:58 +00:00
Chris Lattner
eba719204c revert my fastisel patch again which apparently still gives the 
llvm-gcc-i386-linux-selfhost buildbot heartburn...

llvm-svn: 123431
 2011-01-14 06:14:33 +00:00
Chris Lattner
ee950eeb24 reapply r123414 now that the botz are calmed down and the fix is already in. 
llvm-svn: 123427
 2011-01-14 04:24:28 +00:00
Evan Cheng
0cdd5547f1 Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. 
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.

llvm-svn: 123424
 2011-01-14 02:38:49 +00:00
Chris Lattner
349735530b r123414 broke llvm-gcc bootstrap apparently, revert 
llvm-svn: 123422
 2011-01-14 02:07:32 +00:00
Chris Lattner
5baec05809 fix PR8961 - a fast isel miscompilation where we'd insert a new instruction 
after sext's generated for addressing that got folded.  Previously we compiled
test5 into:

_test5:                                 ## @test5
## BB#0:
        movq    -8(%rsp), %rax          ## 8-byte Reload
        movq    (%rdi,%rax), %rdi
        addq    %rdx, %rdi
        movslq  %esi, %rax
        movq    %rax, -8(%rsp)          ## 8-byte Spill
        movq    %rdi, %rax
        ret

which is insane and wrong.  Now we produce:

_test5:                                 ## @test5
## BB#0:
	movslq	%esi, %rax
	movq	(%rdi,%rax), %rax
	addq	%rdx, %rax
	ret

llvm-svn: 123414
 2011-01-14 00:01:01 +00:00
Owen Anderson
58bcb5d7f2 Recognize alternative register names like ip -> r12. 
Fixes <rdar://problem/8857982>.

llvm-svn: 123409
 2011-01-13 22:50:36 +00:00
Jakob Stoklund Olesen
918de3a3b8 Fix a few more places that should use MBB::getLastNonDebugInstr(). 
llvm-svn: 123408
 2011-01-13 22:47:43 +00:00
Chris Lattner
d2d217dc46 typo 
llvm-svn: 123406
 2011-01-13 22:11:56 +00:00
Chris Lattner
6745cd150c memcpy + metadata = bliss :) 
llvm-svn: 123405
 2011-01-13 22:08:15 +00:00
Owen Anderson
18dfab2332 Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting 
the symbolic immediate names used for these instructions, fixing their pretty-printers, and
adding proper encoding information for them.

With this, we can properly pretty-print and encode assembly like:
	mrc p15, #0, r3, c13, c0, #3

Fixes <rdar://problem/8857858>.

llvm-svn: 123404
 2011-01-13 21:46:02 +00:00
Jakob Stoklund Olesen
0f2b9d9dc4 Teach frame lowering to ignore debug values after the terminators. 
llvm-svn: 123399
 2011-01-13 21:28:52 +00:00
Bob Wilson
569cd41943 Tidy comments, indentation, and 80-column violations. 
llvm-svn: 123397
 2011-01-13 21:10:12 +00:00
Kevin Enderby
eee2f3489b Fix ARMAsmParser::ParseOperand() to allow it to parse . as a branch target and 
directional local labels like 1f and 2b.

llvm-svn: 123393
 2011-01-13 20:32:36 +00:00
Jim Grosbach
767dfbf685 When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctly 
set up the source operands. The original instr has an immediate operand that
should be replaced with the frame reg operand rather than just adding the
reg operand. Previously, the instruction ended up with too many operands
causing an assert() when adding the default predicate. rdar://8825456

llvm-svn: 123387
 2011-01-13 19:16:48 +00:00
Evan Cheng
cc474b4864 Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step 
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.

llvm-svn: 123369
 2011-01-13 07:58:56 +00:00
Eric Christopher
3821f63f4b Experiment with changing the default 32-bit linux stack alignment to 
16 bytes for PR8969. Update all testcases accordingly.

llvm-svn: 123367
 2011-01-13 06:47:10 +00:00
Kevin Enderby
1f82daa2d8 Add a FIXME and two asserts for now in the ARMAsmParser when it sees .code 16 or 
.code 32 if the TargetMachine's isThumb() boolean does not match.  The correct
fix is to switch ARM subtargets at that point and is tracked by rdar://8856789
which is bigger task.

llvm-svn: 123353
 2011-01-13 01:07:01 +00:00
Jason W Kim
af9782e470 Change call to Error() to assert() 
llvm-svn: 123350
 2011-01-13 00:27:00 +00:00
Jason W Kim
5c1d7cc0ca Added clarifying comment 
llvm-svn: 123341
 2011-01-12 23:25:02 +00:00
Jason W Kim
6464be5b92 JimG sez: "The value-kinds look like masks, but they're not consistently used 
that way, unfortunately. If you want to change them to work additively instead
of a one-variant-kind-per-symbolref, that's great and I completely agree it's
worth doing, but it really should be a separate patch. Until then, this isn't
correct."

So I am reverting this bit until a more opportune time.

llvm-svn: 123340
 2011-01-12 23:21:49 +00:00
Bill Wendling
e82361731d Sort the register list based on the *actual* register numbers rather than the 
enum values we give to them. <rdar://problem/8823730>

llvm-svn: 123321
 2011-01-12 21:20:59 +00:00
Matt Beaumont-Gay
fc76b0ce6e Mostly undo r123297, but move the default case in EvaluateAsPCRel to the top 
of the switch block to appease GCC.

llvm-svn: 123317
 2011-01-12 18:02:55 +00:00
Nick Lewycky
fb3f7c11f1 Add another note taken from the gcc bugzilla. 
llvm-svn: 123315
 2011-01-12 09:06:19 +00:00
Venkatraman Govindaraju
2d89fea217 Implement RETURNADDR and FRAMEADDR lowering in SPARC backend. 
llvm-svn: 123310
 2011-01-12 05:08:36 +00:00
Venkatraman Govindaraju
59e9ffc998 Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to 
ensure %o7 is not assigned as the destination of getpcx instruction.

llvm-svn: 123304
 2011-01-12 03:52:59 +00:00
Venkatraman Govindaraju
816f7dfed0 Fix SPARC backend call instruction so that arguments passed through registers 
are correctly marked as used instead of passing all possible argument registers
as used.  

llvm-svn: 123301
 2011-01-12 03:18:21 +00:00
Matt Beaumont-Gay
033b288e84 Prefer llvm_unreachable to assert(0) 
llvm-svn: 123297
 2011-01-12 01:42:42 +00:00
Jason W Kim
ae183f9862 1. Support ELF pcrel relocations for movw/movt: 
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)

llvm-svn: 123294
 2011-01-12 00:19:25 +00:00
Jason W Kim
db6eddeea3 Workaround for bug 8721. 
.s Test added.

llvm-svn: 123292
 2011-01-11 23:53:41 +00:00
Venkatraman Govindaraju
f681d4e782 SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CC 
llvm-svn: 123281
 2011-01-11 22:38:28 +00:00
Evan Cheng
05ef00f4dc Clean up ARM subtarget code by using Triple ADT. 
llvm-svn: 123276
 2011-01-11 21:46:47 +00:00