Commit Graph

16191 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
7513042c0c Add a CoveringSubRegIndices field to SubRegIndex records.
This can be used to tell TableGen to use a specific SubRegIndex instead
of synthesizing one when discovering all sub-registers.

llvm-svn: 161982
2012-08-15 20:15:48 +00:00
Michael J. Spencer
b1010e4913 Properly test the LLVM_USE_RVALUE_REFERENCES macro.
llvm-svn: 161978
2012-08-15 19:16:27 +00:00
Michael J. Spencer
c500bff4cd [PathV2] Add mapped_file_region. Implementation for Windows and POSIX.
llvm-svn: 161976
2012-08-15 19:05:47 +00:00
Michael J. Spencer
60050d27bb Add LLVM_DELETED_FUNCTION compatibility macro.
This should replace uses of:

class A {
  A(const &A); // DO NOT IMPLEMENT
public:
  ...
};

llvm-svn: 161975
2012-08-15 18:54:36 +00:00
Chad Rosier
4f28518fd1 Fix a typo in VariadicFunction.h that leads to invalid code in macro expansion.
Patch by Andy Gibbs <andyg1001@hotmail.co.uk>

llvm-svn: 161973
2012-08-15 18:48:14 +00:00
Bill Wendling
c0ce2ca906 Set the branch probability of branching to the 'normal' destination of an invoke
instruction to something absurdly high, while setting the probability of
branching to the 'unwind' destination to the bare minimum. This should set cause
the normal destination's invoke blocks to be moved closer to the invoke.

PR13612

llvm-svn: 161944
2012-08-15 12:22:35 +00:00
Michael J. Spencer
adb12be31a [yaml2obj] Fix incorrect use of signed values.
llvm-svn: 161900
2012-08-14 22:42:31 +00:00
Jim Grosbach
53796945f5 Switch the fixed-length disassembler to be table-driven.
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
  Previous: 35.5s
  New:       8.9s

TEXT size:
  Previous: 447,251
  New:      297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

llvm-svn: 161888
2012-08-14 19:06:05 +00:00
Richard Smith
937a1cfdad Avoid undefined behavior in DenseMap::shrink_and_clear(). Log2_32_Ceil(0)
returns 32. This change mirrors the corresponding code in
SmallDenseMap::shrink_and_clear().

llvm-svn: 161829
2012-08-14 02:56:51 +00:00
Owen Anderson
c5b77c0317 Add a roundToIntegral method to APFloat, which can be parameterized over various rounding modes. Use this to implement SelectionDAG constant folding of FFLOOR, FCEIL, and FTRUNC.
llvm-svn: 161807
2012-08-13 23:32:49 +00:00
Nadav Rotem
a921b121e2 LICM uses AliasSet information to hoist and sink instructions. However, other passes, such as LoopRotate
may invalidate its AliasSet because SSAUpdater does not update the AliasSet properly.
This patch teaches SSAUpdater to notify AliasSet that it made changes.
The testcase in PR12901 is too big to be useful and I could not reduce it to a normal size. 

rdar://11872059 PR12901

llvm-svn: 161803
2012-08-13 23:06:54 +00:00
Jakob Stoklund Olesen
33e364a3df Remove the TII::scheduleTwoAddrSource() hook.
It never does anything when running 'make check', and it get's in the
way of updating live intervals in 2-addr.

The hook was originally added to help form IT blocks in Thumb2 code
before register allocation, but the pass ordering has changed since
then, and we run if-conversion after register allocation now.

When the MI scheduler is enabled, there will be no less than two
schedulers between 2-addr and Thumb2ITBlockPass, so this hook is
unlikely to help anything.

llvm-svn: 161794
2012-08-13 21:52:57 +00:00
Nadav Rotem
6af514e437 Fix a documentation typo.
llvm-svn: 161758
2012-08-13 15:29:53 +00:00
Craig Topper
3637e6c09d Create isXBitVector methods in MVT and call them from EVT. This allows targets to call them with an MVT without needing to convert to EVT.
llvm-svn: 161731
2012-08-11 23:31:18 +00:00
Eli Bendersky
e4224d8e75 A couple of addition comment fixes
llvm-svn: 161678
2012-08-10 18:30:44 +00:00
Eli Bendersky
1d7189ebcd Fix a couple of typos in comments
llvm-svn: 161677
2012-08-10 18:26:20 +00:00
Rafael Espindola
522e1d0acf Move BasicBlockEdge to the cpp file. No functionality change.
llvm-svn: 161663
2012-08-10 14:05:55 +00:00
Joerg Sonnenberger
f07e1e10a6 Add some missing includes for the build against stdcxx.
llvm-svn: 161657
2012-08-10 10:53:56 +00:00
Rafael Espindola
8a1cdcb7fc Remove references to compression in llvm-ar. It has been a long time since we
switched from a bytecode+bzip2 to the current bitcode.

llvm-svn: 161651
2012-08-10 01:57:52 +00:00
Jakob Stoklund Olesen
5c0e68ae5a Reapply r161633-161634 "Partition use lists so defs always come before uses.""
No changes to these patches, MRI needed to be notified when changing
uses into defs and vice versa.

llvm-svn: 161644
2012-08-10 00:21:30 +00:00
Jakob Stoklund Olesen
b2f9b8589f Also update MRI use lists when changing a use to a def and vice versa.
This was the cause of the buildbot failures.

llvm-svn: 161643
2012-08-10 00:21:26 +00:00
Chad Rosier
b0454bf13e [ms-inline asm] Add a new Inline Asm Non-Standard Dialect attribute.
This new attribute is intended to be used by the backend to determine how
the inline asm string should be parsed/printed. This patch adds the 
ia_nsdialect attribute and also adds a test case to ensure the IR is
correctly parsed, but there is no functional change at this time.

The standard dialect is assumed to be AT&T.  Therefore, this attribute
should only be added to MS-style inline assembly statements, which use
the Intel dialect.  If we ever support more dialects we'll need to
add additional state to the attribute.

llvm-svn: 161641
2012-08-10 00:00:22 +00:00
Jakob Stoklund Olesen
7680d4d42c Revert r161633-161634 "Partition use lists so defs always come before uses."
These commits broke a number of buildbots.

llvm-svn: 161640
2012-08-09 23:31:36 +00:00
Jakob Stoklund Olesen
9594629bf1 Partition use lists so defs always come before uses.
This makes it possible to speed up def_iterator by stopping at the first
use. This makes def_empty() and getUniqueVRegDef() much faster when
there are many uses.

In a +Asserts build, LiveVariables is 100x faster in one case because
getVRegDef() has an assertion that would scan to the end of a
def_iterator chain.

Spill weight calculation is significantly faster (300x in one case)
because isTriviallyReMaterializable() calls MRI->isConstantPhysReg(%RIP)
which calls def_empty(%RIP).

llvm-svn: 161634
2012-08-09 22:49:46 +00:00
Jakob Stoklund Olesen
58b6c3edfa Don't use pointer-pointers for the register use lists.
Use a more conventional doubly linked list where the Prev pointers form
a cycle. This means it is no longer necessary to adjust the Prev
pointers when reallocating the VRegInfo array.

The test changes are required because the register allocation hint is
using the use-list order to break ties.

llvm-svn: 161633
2012-08-09 22:49:42 +00:00
Jakob Stoklund Olesen
c806311dcf Move use list management into MachineRegisterInfo.
Register MachineOperands are kept in linked lists accessible via MRI's
reg_iterator interfaces. The linked list management was handled partly
by MachineOperand methods, partly by MRI methods.

Move all of the list management into MRI, delete
MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo().

Be more explicit about handling the cases where an MRI pointer isn't
available.

llvm-svn: 161632
2012-08-09 22:49:37 +00:00
Chad Rosier
5efd936f43 [ms-inline asm] Extend the MC AsmParser API to match MCInsts (but not emit).
This new API will be used by clang to parse ms-style inline asms.

One goal of this project is to use this style of inline asm for targets other
then x86.  Therefore, this API needs to be implemented for non-x86 targets at
some point in the future.

llvm-svn: 161624
2012-08-09 22:04:55 +00:00
Matt Beaumont-Gay
df72f06088 MachineRegisterInfo was already a friend of MachineOperand, and GCC complains
about repeated friending.

llvm-svn: 161553
2012-08-09 00:30:39 +00:00
Jim Grosbach
dfe45ef6c5 Move [SU]LEB128 encoding to a utility header.
These functions are very generic. There's no reason for them to
be tied to MCObjectWriter.

llvm-svn: 161545
2012-08-08 23:56:06 +00:00
Jakob Stoklund Olesen
074f0ebd26 Move getNextOperandForReg() into MachineRegisterInfo.
MRI provides iterators for traversing the use-def chains. They should
not be accessible from anywhere else.

llvm-svn: 161543
2012-08-08 23:44:07 +00:00
Owen Anderson
822f9fcb08 Allow legalization of target-specific SDNodes, provided that the target itself provide a legalization hook for them.
llvm-svn: 161536
2012-08-08 23:31:14 +00:00
Bill Wendling
55e586387b Remove OpenBSD defines:
- The defines are in stddint.h, which is #include'd already.
- The block wasn't used anyway, since it was _OpenBSD_, and not __OpenBSD__

Patch by David Hill!

llvm-svn: 161515
2012-08-08 18:37:39 +00:00
Andrew Trick
75af469e99 Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

llvm-svn: 161471
2012-08-08 02:44:16 +00:00
Andrew Trick
79c6fbc97e Minor cleanup of defaultDefLatency API
llvm-svn: 161470
2012-08-08 02:44:11 +00:00
Jakob Stoklund Olesen
e89d9ba157 Revert "Fix a quadratic algorithm in MachineBranchProbabilityInfo."
It caused an assertion failure when compiling consumer-typeset.

llvm-svn: 161463
2012-08-08 01:10:31 +00:00
Jakob Stoklund Olesen
10c3144381 Fix a quadratic algorithm in MachineBranchProbabilityInfo.
The getSumForBlock function was quadratic in the number of successors
because getSuccWeight would perform a linear search for an already known
iterator.

llvm-svn: 161460
2012-08-08 00:20:37 +00:00
Jakob Stoklund Olesen
3c221664e3 Add SelectionDAG::getTargetIndex.
This adds support for TargetIndex operands during isel. The meaning of
these (index, offset, flags) operands is entirely defined by the target.

llvm-svn: 161453
2012-08-07 22:37:05 +00:00
Jakob Stoklund Olesen
301af79343 Add a new kind of MachineOperand: MO_TargetIndex.
A target index operand looks a lot like a constant pool reference, but
it is completely target-defined. It contains the 8-bit TargetFlags, a
32-bit index, and a 64-bit offset. It is preserved by all code generator
passes.

TargetIndex operands can be used to carry target-specific information in
cases where immediate operands won't suffice.

llvm-svn: 161441
2012-08-07 18:56:39 +00:00
Rafael Espindola
ccfbbaa11f The dominance computation already has logic for computing if an edge dominates
a use or a BB, but it is inline in the handling of the invoke instruction.

This patch refactors it so that it can be used in other cases. For example, in

define i32 @f(i32 %x) {
bb0:
  %cmp = icmp eq i32 %x, 0
  br i1 %cmp, label %bb2, label %bb1
bb1:
  br label %bb2
bb2:
  %cond = phi i32 [ %x, %bb0 ], [ 0, %bb1 ]
  %foo = add i32 %cond, %x
  ret i32 %foo
}

GVN should be able to replace %x with 0 in any use that is dominated by the
true edge out of bb0. In the above example the only such use is the one in
the phi.

llvm-svn: 161429
2012-08-07 17:30:46 +00:00
Bill Wendling
69f9777937 Revert r161371. Removing the 'const' before Type is a "good thing".
--- Reverse-merging r161371 into '.':
U    include/llvm/Target/TargetData.h
U    lib/Target/TargetData.cpp

llvm-svn: 161394
2012-08-07 05:51:59 +00:00
Bill Wendling
dc532577fd Constify the Type parameter to some methods (which are const anyway).
llvm-svn: 161371
2012-08-07 00:26:35 +00:00
Jakob Stoklund Olesen
8d107f3948 Fix typo.
llvm-svn: 161354
2012-08-06 22:34:51 +00:00
Eric Christopher
f5132794cd Add support for the OpenBSD for Bitrig.
Patch by David Hill.

llvm-svn: 161344
2012-08-06 20:52:18 +00:00
Simon Atanasyan
03f8384c4e Fix MIPS DSP Rev1 intrinsics memory properties.
The patch reviewed by Akira Hatanaka.

llvm-svn: 161332
2012-08-06 19:47:47 +00:00
Jakob Stoklund Olesen
2bb405a329 Put up warning signs around MO::getNextOperandForReg().
llvm-svn: 161329
2012-08-06 18:48:43 +00:00
Hal Finkel
aadd19de06 Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.

llvm-svn: 161302
2012-08-04 14:10:46 +00:00
Jakob Stoklund Olesen
14c88af5f2 Add an experimental -early-live-intervals option.
This option runs LiveIntervals before TwoAddressInstructionPass which
will eventually learn to exploit and update the analysis.

Eventually, LiveIntervals will run before PHIElimination, and we can get
rid of LiveVariables.

llvm-svn: 161270
2012-08-03 22:12:54 +00:00
Bob Wilson
7e2fb62620 Try to reduce the compile time impact of r161232.
The previous change caused fast isel to not attempt handling any calls to
builtin functions.  That included things like "printf" and caused some
noticable regressions in compile time.  I wanted to avoid having fast isel
keep a separate list of functions that had to be kept in sync with what the
code in SelectionDAGBuilder.cpp was handling.  I've resolved that here by
moving the list into TargetLibraryInfo.  This is somewhat redundant in
SelectionDAGBuilder but it will ensure that we keep things consistent.

llvm-svn: 161263
2012-08-03 21:26:24 +00:00
Jakob Stoklund Olesen
bf7a000191 Completely eliminate VNInfo flags.
The 'unused' state of a value number can be represented as an invalid
def SlotIndex. This also exposed code that shouldn't have been looking
at unused value VNInfos.

llvm-svn: 161258
2012-08-03 20:59:32 +00:00
Jakob Stoklund Olesen
38aec46f18 Eliminate the VNInfo::hasPHIKill() flag.
The only real user of the flag was removeCopyByCommutingDef(), and it
has been switched to LiveIntervals::hasPHIKill().

All the code changed by this patch was only concerned with computing and
propagating the flag.

llvm-svn: 161255
2012-08-03 20:19:44 +00:00