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39595 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
83ab844c9b Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass. 
INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

llvm-svn: 107726
 2010-07-06 23:26:25 +00:00
Jakob Stoklund Olesen
44c333e87c Track defs for all aliases in NEONMoveFix. 
This means that an instruction defining an S register will affect the domain of
the parent D register.

llvm-svn: 107725
 2010-07-06 23:26:23 +00:00
Bruno Cardoso Lopes
b9e1c33054 Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107723
 2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
0c6ec0b068 Add part of AVX SSE4.1 packed move with sign/zero extend instructions 
llvm-svn: 107720
 2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
af8968696a Fix comment from previous patch 
llvm-svn: 107717
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes
a0b37e839c Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Dan Gohman
d409104054 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext. 
SelectBasicBlock doesn't needs its BasicBlock argument.

llvm-svn: 107712
 2010-07-06 22:19:37 +00:00
Devang Patel
7ab104353b Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Bob Wilson
084a11cb59 Represent NEON load/store alignments in bytes, not bits. 
llvm-svn: 107701
 2010-07-06 21:26:18 +00:00
Jakob Stoklund Olesen
bc4a57ef56 One more case assuming that subregs have live ranges. 
llvm-svn: 107700
 2010-07-06 21:13:03 +00:00
Jakob Stoklund Olesen
ec2c876e57 Fix buildbot breakage where a def is missing. 
llvm-svn: 107698
 2010-07-06 21:06:39 +00:00
Devang Patel
568037d823 Add fixme. 
llvm-svn: 107697
 2010-07-06 21:05:17 +00:00
Jakob Stoklund Olesen
f86de96f78 Be more forgiving when calculating alias interference for physreg coalescing. 
It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.

This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.

llvm-svn: 107695
 2010-07-06 20:31:51 +00:00
Dan Gohman
808f334f79 Reapply r107655 with fixes; insert the pseudo instruction into 
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

llvm-svn: 107691
 2010-07-06 20:24:04 +00:00
Eric Christopher
383df15267 Fix to 80-col. 
llvm-svn: 107684
 2010-07-06 18:35:20 +00:00
Devang Patel
ffc54b23fe Fix PR7545 crash. 
llvm-svn: 107678
 2010-07-06 18:18:32 +00:00
Rafael Espindola
e5689571a1 Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion 
if profitable.

llvm-svn: 107673
 2010-07-06 16:24:34 +00:00
Chris Lattner
18ba4703b0 tighten up this code. 
llvm-svn: 107670
 2010-07-06 15:59:27 +00:00
Dan Gohman
4d264f7e51 Revert r107655. 
llvm-svn: 107668
 2010-07-06 15:49:48 +00:00
Dan Gohman
38f2820fc3 Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands 
which do not depend on SelectionDAG.

llvm-svn: 107666
 2010-07-06 15:39:54 +00:00
Dan Gohman
c88c36181f Make getMinimalPhysRegClass' comment mention what makes it different 
from getPhysicalRegisterRegClass.

llvm-svn: 107660
 2010-07-06 15:31:55 +00:00
Anton Korobeynikov
3097e49515 Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards. 
This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc').

llvm-svn: 107658
 2010-07-06 15:24:56 +00:00
Dan Gohman
0cea029f14 Add some more TODO comments. 
llvm-svn: 107657
 2010-07-06 15:23:00 +00:00
Dan Gohman
fa0252225f Add a comment. 
llvm-svn: 107656
 2010-07-06 15:21:57 +00:00
Dan Gohman
6a73079aba Fix a bunch of custom-inserter functions to handle the case where 
the pseudo instruction is not at the end of the block.

llvm-svn: 107655
 2010-07-06 15:18:19 +00:00
Eric Christopher
e873e9978c Fix up -fstack-protector on linux to use the segment 
registers.  Split out testcases per architecture and os
now.

Patch from Nelson Elhage.

llvm-svn: 107640
 2010-07-06 05:18:56 +00:00
Nick Lewycky
16490a3bf1 Detabify this file. 
llvm-svn: 107637
 2010-07-06 03:53:43 +00:00
Eric Christopher
f1bb5da020 Have the X86 backend use Triple instead of a string and some enums. 
llvm-svn: 107625
 2010-07-05 19:26:33 +00:00
Kalle Raiskila
59cf410bf5 Remove some unused/redundant code. 
llvm-svn: 107622
 2010-07-05 18:40:09 +00:00
Chris Lattner
252f82acc6 more tidying. 
llvm-svn: 107615
 2010-07-05 05:53:14 +00:00
Chris Lattner
6a9b6e3253 some notes about suboptimal insertps's 
llvm-svn: 107613
 2010-07-05 05:48:41 +00:00
Chris Lattner
bbc150b397 random tidying 
llvm-svn: 107612
 2010-07-05 05:36:21 +00:00
Chris Lattner
e7c95bcd9e rip out even more sporadic v2f32 support. 
llvm-svn: 107610
 2010-07-05 04:38:33 +00:00
Chris Lattner
82c3b22a55 rip out the various v2f32 "mmx" handling logic, now that 
v2f32 is illegal on x86.

llvm-svn: 107609
 2010-07-05 04:36:27 +00:00
Jakob Stoklund Olesen
9b1eb2b2ac Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG. 
llvm-svn: 107602
 2010-07-04 23:24:23 +00:00
Chris Lattner
cecaa1b061 Just rip v2f32 support completely out of the X86 backend. In 
the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 

llvm-svn: 107601
 2010-07-04 23:07:25 +00:00
Chris Lattner
b17c4f3936 fix PR7518 - terrible codegen of <2 x float>, by only marking 
v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

llvm-svn: 107600
 2010-07-04 22:57:10 +00:00
Chris Lattner
1e38d7d66d indentation 
llvm-svn: 107599
 2010-07-04 22:56:10 +00:00
Evan Cheng
9604b825a4 Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments. 
llvm-svn: 107591
 2010-07-04 18:52:05 +00:00
Bill Wendling
689155c673 Revert r107583. I no longer think that this is the way to solve the problem. 
llvm-svn: 107585
 2010-07-04 09:16:57 +00:00
Bill Wendling
8a3ecba7a4 Mark sse_load_f32 and sse_load_f64 as having memory operands 
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.

llvm-svn: 107583
 2010-07-04 08:59:55 +00:00
Bill Wendling
34feb1390d Proper indentation. 
llvm-svn: 107581
 2010-07-04 08:58:43 +00:00
Eli Friedman
4cac2d90a2 Minor amendment to switch-lowering improvement. 
llvm-svn: 107569
 2010-07-03 08:43:32 +00:00
Eli Friedman
663bc3ce7e Note switch-lowering inefficiency. 
llvm-svn: 107565
 2010-07-03 07:38:12 +00:00
Bruno Cardoso Lopes
dc16024895 Add AVX SSE4.1 blend, mpsadbw and vdp 
llvm-svn: 107560
 2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
9cbb625579 Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions 
llvm-svn: 107558
 2010-07-03 01:15:47 +00:00
Eric Christopher
ab076a2261 Fix typo. 
llvm-svn: 107556
 2010-07-03 01:09:18 +00:00
Bruno Cardoso Lopes
df02d037e4 Add AVX SSE4.1 Horizontal Minimum and Position instruction 
llvm-svn: 107552
 2010-07-03 00:49:21 +00:00
Evan Cheng
47f3a2db40 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. 
llvm-svn: 107550
 2010-07-03 00:40:23 +00:00
Bruno Cardoso Lopes
e6b70efcb0 Add AVX SSE4.1 round instructions 
llvm-svn: 107549
 2010-07-03 00:37:44 +00:00