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852a9caebd
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19318 Commits

Author SHA1 Message Date
Akira Hatanaka
852a9caebd Do not examine variadic or implicit operands if instruction is a return (jr). 
llvm-svn: 141157
 2011-10-05 02:21:58 +00:00
Akira Hatanaka
eb59ca6c4c Clean up function Filler::delayHasHazard. 
llvm-svn: 141156
 2011-10-05 02:18:58 +00:00
Akira Hatanaka
1d80eaba44 Remove function Filler::insertCallUses. 
Record the registers used and defined by a call in Filler::insertDefsUses.

llvm-svn: 141154
 2011-10-05 02:04:17 +00:00
Akira Hatanaka
3707b9fec8 Clean up Filler::findDelayInstr. 
llvm-svn: 141152
 2011-10-05 01:57:46 +00:00
Akira Hatanaka
594683f3d7 Remove function Filler::isDelayFiller. Check if I is the same instruction that 
filled the last delay slot visited.

llvm-svn: 141151
 2011-10-05 01:30:09 +00:00
Akira Hatanaka
6698bae640 Clean up Filler::runOnMachineBasicBlock. Change interface of 
Filler::findDelayInstr.

llvm-svn: 141150
 2011-10-05 01:23:39 +00:00
Akira Hatanaka
716e3bea9c Define a statistic for the number of slots that were filled with useful 
instructions (instructions that are not NOP).

llvm-svn: 141149
 2011-10-05 01:19:13 +00:00
Akira Hatanaka
c073bd7709 Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before 
I->getDesc().hasDelaySlot() does.

llvm-svn: 141148
 2011-10-05 01:15:31 +00:00
Akira Hatanaka
cf11c1bfbe Add comments and move assignment statement. If sawStore is true, sawLoad does 
not have to be set.

llvm-svn: 141147
 2011-10-05 01:09:37 +00:00
Akira Hatanaka
58d3445fd9 Correct description string of enable-mips-delay-filler. 
llvm-svn: 141146
 2011-10-05 01:06:57 +00:00
Bill Wendling
da6fd6f972 Look at the number of entries in the jump table and jump to a 'trap' block if 
the value exceeds that number.

llvm-svn: 141143
 2011-10-05 00:39:32 +00:00
Bill Wendling
db8e0d2dee Checkpoint for SJLJ EH code. 
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.

llvm-svn: 141140
 2011-10-05 00:02:33 +00:00
Owen Anderson
e255773f3d Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. 
llvm-svn: 141135
 2011-10-04 23:26:17 +00:00
Kevin Enderby
5a09a8db55 Adding back support for printing operands symbolically to ARM's new disassembler 
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129
 2011-10-04 22:44:48 +00:00
Jakob Stoklund Olesen
0d68d7507e Teach PPCInstrInfo to handle sub-classes. 
This has already been done for most other targets.

llvm-svn: 141083
 2011-10-04 15:28:47 +00:00
Nadav Rotem
a2dd9646d8 Set operation actions to legal types only. 
llvm-svn: 141075
 2011-10-04 12:05:35 +00:00
Nadav Rotem
c4ed7cd5f2 Operations should be custom lowered only if their type is legal. 
Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074
 2011-10-04 10:03:32 +00:00
Craig Topper
9d32602cfd Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Jim Grosbach
f38874e79e ARM assembly parsing and encoding for VMOV immediate. 
llvm-svn: 141046
 2011-10-03 23:38:36 +00:00
Jim Grosbach
5723a6f6ea Tidy up. 80 columns. 
llvm-svn: 141043
 2011-10-03 23:03:26 +00:00
Bill Wendling
68ee098b5a Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it. 
llvm-svn: 141042
 2011-10-03 22:44:15 +00:00
Jim Grosbach
c69258c747 ARM parsing/encoding for VCMP/VCMPE. 
llvm-svn: 141038
 2011-10-03 22:30:24 +00:00
Bill Wendling
834bb83a41 Check-pointing the new SjLj EH lowering. 
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.

llvm-svn: 141031
 2011-10-03 21:25:38 +00:00
Akira Hatanaka
76c268271d Add support for 64-bit logical NOR. 
llvm-svn: 141029
 2011-10-03 21:23:18 +00:00
Akira Hatanaka
ae50204423 Add support for 64-bit count leading ones and zeros instructions. 
llvm-svn: 141028
 2011-10-03 21:16:50 +00:00
Jim Grosbach
21a9f8f50f ARM assembly parsing and encoding for VMRS/FMSTAT. 
llvm-svn: 141025
 2011-10-03 21:12:43 +00:00
Akira Hatanaka
6c6ff6fde7 Add support for 64-bit divide instructions. 
llvm-svn: 141024
 2011-10-03 21:06:13 +00:00
Jim Grosbach
c7a9669343 Thumb2 ADD/SUB can take SP as a destination register. 
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.

llvm-svn: 141020
 2011-10-03 20:51:59 +00:00
Akira Hatanaka
7e1775fdd6 Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer 
registers.

llvm-svn: 141019
 2011-10-03 20:38:08 +00:00
Akira Hatanaka
e3c1d7eac0 Add support for 64-bit integer multiply instructions. 
llvm-svn: 141017
 2011-10-03 20:01:11 +00:00
Akira Hatanaka
3f3d72c052 Add definitions of instructions which move values between 64-bit integer 
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.

llvm-svn: 141015
 2011-10-03 19:28:44 +00:00
Craig Topper
df04bee9b2 Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. 
llvm-svn: 141007
 2011-10-03 17:28:23 +00:00
Rafael Espindola
4700f53cee Add the returns_twice attribute to LLVM. 
llvm-svn: 141001
 2011-10-03 14:45:37 +00:00
Craig Topper
4456c94f70 Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode. 
llvm-svn: 140997
 2011-10-03 08:14:29 +00:00
Craig Topper
7a5eafab6c Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode. 
llvm-svn: 140993
 2011-10-03 07:51:09 +00:00
Craig Topper
f776e3b410 Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. 
llvm-svn: 140974
 2011-10-02 21:08:12 +00:00
Craig Topper
5c8feca34f Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344. 
llvm-svn: 140971
 2011-10-02 16:56:09 +00:00
Craig Topper
43fd621df8 Fix disassembling of INVEPT and INVVPID to take operands 
llvm-svn: 140955
 2011-10-01 21:20:14 +00:00
Craig Topper
99ad3cc23e Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
llvm-svn: 140954
 2011-10-01 19:54:56 +00:00
Chad Rosier
2cb0d1eddf Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." 
to appease nightly testers.  Not quite there yet.

llvm-svn: 140953
 2011-10-01 19:30:36 +00:00
Bill Wendling
d6d232142d No one should be using the method directly. Assert if they do. 
llvm-svn: 140947
 2011-10-01 12:47:34 +00:00
Bill Wendling
3ce912d5b8 Add a convenience method to tell if two things are equal. 
llvm-svn: 140946
 2011-10-01 12:44:28 +00:00
Bill Wendling
a23068ec02 Use the ARMConstantPoolMBB class to handle the MBB values. 
llvm-svn: 140943
 2011-10-01 09:30:42 +00:00
Bill Wendling
a925d1339f Add ARMConstantPoolMBB to hold an MBB value in the constant pool. 
llvm-svn: 140942
 2011-10-01 09:19:10 +00:00
Bill Wendling
aab50632f6 Remove dead code. 
llvm-svn: 140941
 2011-10-01 09:05:12 +00:00
Bill Wendling
0049e4398d Remove now dead methods and ivar. 
llvm-svn: 140940
 2011-10-01 09:04:18 +00:00
Bill Wendling
c7bf6da86d Use the new ARMConstantPoolSymbol class to handle external symbols. 
llvm-svn: 140939
 2011-10-01 08:58:29 +00:00
Bill Wendling
4563d806a7 Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class. 
llvm-svn: 140938
 2011-10-01 08:36:59 +00:00
Bill Wendling
67b6d8a185 Remove now dead methods and ivar from ARMConstantPoolValue. 
llvm-svn: 140937
 2011-10-01 08:02:05 +00:00
Bill Wendling
1d585d7961 Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.

llvm-svn: 140936
 2011-10-01 08:00:54 +00:00