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3895 Commits

Author SHA1 Message Date
Christopher Lamb
8875f43912 Implement review feedback. No functionality change. 
llvm-svn: 40863
 2007-08-06 16:33:56 +00:00
Reid Spencer
3e54e72ef1 Fix minor doxygen nits. 
llvm-svn: 40854
 2007-08-05 20:06:04 +00:00
Chris Lattner
bc90e7255f shorten this name 
llvm-svn: 40843
 2007-08-05 18:45:33 +00:00
Chandler Carruth
00e56b0e81 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. 
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807
 2007-08-04 01:51:18 +00:00
Dan Gohman
352de5aeb9 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Chris Lattner
9319dfc93a don't redefine a parameter 
llvm-svn: 40748
 2007-08-02 18:08:16 +00:00
Evan Cheng
a06b9cf09f Do not emit copies for physical register output if it's not used. 
llvm-svn: 40722
 2007-08-02 05:29:38 +00:00
Scott Michel
199544367f Style police: Expand the tabs to spaces! 
llvm-svn: 40712
 2007-08-02 02:22:46 +00:00
Evan Cheng
14bd520741 Instead of adding copyfromreg's to handle physical definitions. Now isel can 
simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)

Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)

And let scheduledag emit the move from X86::EAX to a virtual register.

llvm-svn: 40710
 2007-08-02 00:28:15 +00:00
Evan Cheng
d6d66f0cf4 Bugs: missing partial uses and redundant partial defs. 
llvm-svn: 40688
 2007-08-01 20:18:21 +00:00
Lauro Ramos Venancio
1ef30713de Expand unaligned loads/stores when the target doesn't support them. (PR1548) 
llvm-svn: 40682
 2007-08-01 19:34:21 +00:00
David Greene
f06a395bb9 New CallInst interface to address GLIBCXX_DEBUG errors caused by 
indexing an empty std::vector.

Updates to all clients.

llvm-svn: 40660
 2007-08-01 03:43:44 +00:00
Evan Cheng
8889a56947 simpleregistercoalescing -> regcoalescing. It's too long for me to handle. 
llvm-svn: 40654
 2007-07-31 22:37:44 +00:00
Scott Michel
c65b4c8eeb - Allow custom lowering for CTPOP, CTTZ, CTLZ. 
- Fixed an existing unexpanded tab.

llvm-svn: 40605
 2007-07-30 21:00:31 +00:00
Dan Gohman
375d541183 Fix a bug in getCopyFromParts turned up in the testcase for PR1132. 
llvm-svn: 40598
 2007-07-30 19:09:17 +00:00
Dan Gohman
555f611994 Print a space between the comment character and the basic block name, 
for prettiness.

llvm-svn: 40593
 2007-07-30 15:06:25 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Christopher Lamb
55a1e36013 Move subreg lowering pass to be right after regalloc, per feedback. 
llvm-svn: 40548
 2007-07-27 07:36:14 +00:00
Dan Gohman
249090568d Fix the alias analysis query in DAGCombiner to not add in two 
offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.

llvm-svn: 40534
 2007-07-26 16:14:06 +00:00
Christopher Lamb
258dab5389 Add a MachineFunction pass, which runs post register allocation, that turns subreg insert/extract instruction into register copies. This ensures correct code gen if the coalescer isn't able to remove all subreg instructions. 
llvm-svn: 40521
 2007-07-26 08:18:32 +00:00
Christopher Lamb
08bcd5c0f8 Teach DAG scheduling how to properly emit subreg insert/extract machine instructions. PR1350 
llvm-svn: 40520
 2007-07-26 08:12:07 +00:00
Christopher Lamb
73c3cd47cc Add selection DAG nodes for subreg insert/extract. PR1350 
llvm-svn: 40516
 2007-07-26 07:34:40 +00:00
Christopher Lamb
cb63a77a51 Remove subreg index from MachineInstr's and also keep vregs as unsigned when adding operands. 
llvm-svn: 40514
 2007-07-26 07:00:46 +00:00
Christopher Lamb
b178ecbbc0 Fix infinite recursion for when extract_vector_elt is legal. Unfortunately no public targets use this code-path, so no test. 
llvm-svn: 40510
 2007-07-26 03:33:13 +00:00
Evan Cheng
4b747bb6a0 EmitAlignment() also emits optional fill value. 
llvm-svn: 40500
 2007-07-25 23:35:07 +00:00
Anton Korobeynikov
e0344393bb Minor cleanup: 
- Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481
 2007-07-25 00:06:28 +00:00
Dan Gohman
1444c5840b Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask. 
llvm-svn: 40480
 2007-07-24 23:00:27 +00:00
Dan Gohman
54b8032d64 Fix some uses of dyn_cast to be uses of cast. 
llvm-svn: 40443
 2007-07-23 20:24:29 +00:00
Dan Gohman
ac8ccab48f Don't assume that only Uses can be kills. Defs are marked as kills initially 
when there are no uses. This fixes a dangling-pointer bug, where pointers to
deleted instructions were not removed from kills lists. More info here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-July/009749.html

llvm-svn: 40131
 2007-07-20 23:17:34 +00:00
Evan Cheng
cdb4e7949f Added -print-emitted-asm to print out JIT generated asm to cerr. 
llvm-svn: 40123
 2007-07-20 21:56:13 +00:00
Duncan Sands
840594467f As pointed out by g++-4.2, the original code didn't do 
what it thought it was doing.

llvm-svn: 40044
 2007-07-19 07:31:58 +00:00
Evan Cheng
5dd17373c5 Add comment. 
llvm-svn: 40022
 2007-07-18 23:34:48 +00:00
Dan Gohman
4c140b7128 It's not necessary to do rounding for alloca operations when the requested 
alignment is equal to the stack alignment.

llvm-svn: 40004
 2007-07-18 16:29:46 +00:00
Evan Cheng
6ad7064bdf Dead code. 
llvm-svn: 39979
 2007-07-17 20:01:19 +00:00
Dan Gohman
0ba554c0c8 Fix comments about vectors to use the current wording. 
llvm-svn: 39921
 2007-07-16 14:29:03 +00:00
Nick Lewycky
05e4170839 Fix the build. Patch from Holger Schurig. 
llvm-svn: 39856
 2007-07-14 15:11:14 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Dan Gohman
44771cf8e8 Fix the comment for LegalizeOp to more accurately reflect what it does. 
llvm-svn: 39827
 2007-07-13 20:14:11 +00:00
Dan Gohman
1f4580ceb4 Don't call SimplifyVBinOp for non-vector operations, following earlier review 
feedback. This theoretically makes the common (scalar) case more efficient.

llvm-svn: 39823
 2007-07-13 20:03:40 +00:00
Dale Johannesen
1a9d304c35 Modify previous patch per review comments. 
llvm-svn: 39817
 2007-07-13 17:31:29 +00:00
Dale Johannesen
469ed8e17e Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816
 2007-07-13 17:13:54 +00:00
Duncan Sands
b2a18dc10b The type ids making up a filter are unsigned, and 
should be output as unsigned values.  Checked against
gcc.

llvm-svn: 39775
 2007-07-12 13:51:39 +00:00
Evan Cheng
c7216b3a86 Missed a couple of places where new instructions are added due to spill / restore. 
llvm-svn: 39748
 2007-07-11 19:17:18 +00:00
Duncan Sands
bfbe683782 Exception handling has been implemented. 
llvm-svn: 39732
 2007-07-11 16:59:20 +00:00
Duncan Sands
aa83dc9037 If assertions are not enabled, we should return False here. 
llvm-svn: 38535
 2007-07-11 08:47:55 +00:00
Evan Cheng
2791a7ea6d No longer need to track last def / use. 
llvm-svn: 38534
 2007-07-11 08:47:44 +00:00
Evan Cheng
c42a2e03f1 Fix for PR1545: Revamp code that update kill information due to register reuse. 
llvm-svn: 38525
 2007-07-11 05:28:39 +00:00
David Greene
8d77dcca00 Make this work with GLIBCXX_DEBUG. 
llvm-svn: 38516
 2007-07-10 22:00:30 +00:00
Dan Gohman
629311ca52 Change the peep for EXTRACT_VECTOR_ELT of BUILD_PAIR to look for 
the new CONCAT_VECTORS node type instead, as that's what legalize
uses now. And add a peep for EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT.

llvm-svn: 38503
 2007-07-10 18:20:44 +00:00
Evan Cheng
d80c2821af If the operand is marked M_OPTIONAL_DEF_OPERAND, then it's a def. 
llvm-svn: 38496
 2007-07-10 17:52:20 +00:00