Stanislav Mekhanoshin
b2de8bbb4a
[AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32
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Differential Revision: https://reviews.llvm.org/D41617
llvm-svn: 322500
2018-01-15 18:49:15 +00:00
Matt Arsenault
426c222888
AMDGPU: Remove -mcpu=SI
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Leftover from before amdgcn/r600 split.
llvm-svn: 310277
2017-08-07 18:30:35 +00:00
Dmitry Preobrazhensky
632c5467cb
[AMDGPU][MC] Added check for truncation of SOPK imm operand
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See bug 30827: https://bugs.llvm.org//show_bug.cgi?id=30827
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D32535
llvm-svn: 301418
2017-04-26 15:34:19 +00:00
Artem Tamazov
0b6855273a
[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.
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Possibility to specify code of hardware register kept.
Disassemble to symbolic name, if name is known.
Tests updated/added.
Differential Revision: http://reviews.llvm.org/D19335
llvm-svn: 267724
2016-04-27 15:17:03 +00:00
Artem Tamazov
7fa01faba1
[AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.
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Added hwreg(reg[,offset,width]) syntax.
Default offset = 0, default width = 32.
Possibility to specify 16-bit immediate kept.
Added out-of-range checks.
Disassembling is always to hwreg(...) format.
Tests updated/added.
Differential Revision: http://reviews.llvm.org/D19329
llvm-svn: 267410
2016-04-25 14:13:51 +00:00
Artem Tamazov
cc6f4e6962
[AMDGPU][llvm-mc] s_setreg* - Fix order of operands
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Order should match the sp3 syntax, where destination (simm16 denoting the hwreg) is coming first.
Differential Revision: http://reviews.llvm.org/D19161
llvm-svn: 266617
2016-04-18 14:54:26 +00:00
Nikolay Haustov
ebb90e5bf2
[AMDGPU] Assembler: Update SOP* tests
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Add VI encodings.
Reformat sopp.s to match style of other files.
Differential Revision: http://reviews.llvm.org/D18084
llvm-svn: 263540
2016-03-15 07:44:57 +00:00
Tom Stellard
3f1708598e
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
