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438 Commits

Author SHA1 Message Date
Dale Johannesen
8c1e95810f Use ## for comment delimiter on darwin x86-32, so 
llvm's output .s files will go through gcc -std=c99
without triggering preprocesser errors.  Approach
suggested by Daveed Vandevoorde.

llvm-svn: 48808
 2008-03-25 23:29:30 +00:00
Evan Cheng
8cb64d8e8b Handle a special case xor undef, undef -> 0. Technically this should be transformed to undef. But this is such a common idiom (misuse) we are going to handle it. 
llvm-svn: 48792
 2008-03-25 20:08:07 +00:00
Dan Gohman
58ad056286 Add CMP32mr and friends to the load-unfolding table. Among 
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.

llvm-svn: 48777
 2008-03-25 16:53:19 +00:00
Tanya Lattner
b6a27ed83f Byebye llvm-upgrade! 
llvm-svn: 48762
 2008-03-25 04:26:08 +00:00
Evan Cheng
dbdf48276a - SSE4.1 extractfps extracts a f32 into a gr32 register. Very useful! Not. Fix the instruction specification and teaches lowering code to use it only when the only use is a store instruction. 
llvm-svn: 48746
 2008-03-24 21:52:23 +00:00
Dan Gohman
b9c5e6258f APIntify SelectionDAG's EXTRACT_ELEMENT code. 
llvm-svn: 48726
 2008-03-24 16:38:05 +00:00
Evan Cheng
874aee2eec Teach DAG combiner to commute commutable binary nodes in order to achieve sdisel CSE. 
llvm-svn: 48673
 2008-03-22 01:55:50 +00:00
Dan Gohman
59aeac6320 Handle getresult instructions in different basic blocks 
from their aggregate operands by moving the getresult
instructions.

llvm-svn: 48657
 2008-03-21 21:01:32 +00:00
Chris Lattner
8a4fa95cae Add support for calls that return two FP values in 
ST(0)/ST(1).

llvm-svn: 48634
 2008-03-21 06:38:26 +00:00
Chris Lattner
933d0d318b disable a bogus assertion. 
llvm-svn: 48633
 2008-03-21 06:01:05 +00:00
Chris Lattner
260473f983 Enable support for returning two long-double values in ST(0)/ST(1). 
This allows us to compile fp-stack-2results.ll into:

_test:
	fldz
	fld1
	ret

which returns 1 in ST(0) and 0 in ST(1).  This is needed for x86-64
_Complex long double.

llvm-svn: 48632
 2008-03-21 05:57:20 +00:00
Evan Cheng
4ae9fee64c Undo 48570. Correctly match mmx shift instructions with an immediate operand. 
llvm-svn: 48627
 2008-03-21 00:40:09 +00:00
Evan Cheng
8ecb189245 Fix this xform: (sra (shl X, m), result_size) -> (sign_extend (trunc (shl X, result_size - n - m))) 
llvm-svn: 48578
 2008-03-20 02:18:41 +00:00
Evan Cheng
6f729b2820 Add intrinsics to match mmx shift builtin's with immediate operand. 
llvm-svn: 48569
 2008-03-19 23:38:52 +00:00
Christopher Lamb
958b0494c3 Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491. 
llvm-svn: 48542
 2008-03-19 08:30:06 +00:00
Evan Cheng
e9aa507edc Fixed a coalescer bug caused by a typo. 
llvm-svn: 48526
 2008-03-19 02:26:36 +00:00
Evan Cheng
3d9309c11d Fix live variables issues: 
1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue.
2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register:
   = EAX, AX<imp-use,kill>
...
AX =
In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things.

llvm-svn: 48521
 2008-03-19 00:52:20 +00:00
Evan Cheng
5ac87b837e Fix a x86-64 isel lowering bug that's been around forever. A x86-64 varargs function implicitly reads X86::AL, don't clobber it! 
llvm-svn: 48515
 2008-03-18 23:36:35 +00:00
Bill Wendling
c8f3fc7c3d It might be nice to have this run as x86 on non-x86 platforms... 
llvm-svn: 48511
 2008-03-18 22:38:22 +00:00
Bill Wendling
5ea2aec3ac Temporarily revert r48491. It's breaking test/CodeGen/X86/xorl.ll. 
llvm-svn: 48510
 2008-03-18 22:29:51 +00:00
Christopher Lamb
1d70509b55 Target independent DAG transform to use truncate for field extraction + sign extend on targets where this is profitable. Passes nightly on x86-64. 
llvm-svn: 48491
 2008-03-18 16:46:39 +00:00
Chris Lattner
bb335409c2 ensure we continue matching x86-64 rotates. 
llvm-svn: 48437
 2008-03-17 01:35:03 +00:00
Evan Cheng
3612a7ed30 Fix PR2138. Apparently any modification to a std::multimap (including remove entries for a different key) can invalidate multimap iterators. 
llvm-svn: 48371
 2008-03-14 20:44:01 +00:00
Evan Cheng
53c3dd0267 New test case. 
llvm-svn: 48338
 2008-03-13 08:05:02 +00:00
Evan Cheng
a76bb6e64e A test case I forgot to check in. 
llvm-svn: 48335
 2008-03-13 06:42:46 +00:00
Evan Cheng
0b8b1647dd TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one. 
llvm-svn: 48333
 2008-03-13 06:37:55 +00:00
Evan Cheng
620fd19798 Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: 
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!

llvm-svn: 48307
 2008-03-12 22:19:41 +00:00
Dan Gohman
2ec41788ab Fix this test on hosts that don't have sse2. 
llvm-svn: 48296
 2008-03-12 20:40:51 +00:00
Dan Gohman
2a124430e9 Make this test x86-specific for now; targets that don't use 
the automated CallingConv code to handle return values typically
don't support multiple return values.

llvm-svn: 48265
 2008-03-12 00:25:14 +00:00
Anton Korobeynikov
d2fd135594 Testcase for PR2137 
llvm-svn: 48258
 2008-03-11 22:43:42 +00:00
Anton Korobeynikov
efa9405b94 Update testcase for recent aliases change 
llvm-svn: 48250
 2008-03-11 21:42:20 +00:00
Dan Gohman
f9f25bd41b Add a test to ensure that all-ones vectors are materialized with pcmpeqd. 
llvm-svn: 48247
 2008-03-11 21:37:00 +00:00
Dan Gohman
1fece90de9 Use the correct value for InSignBit. 
llvm-svn: 48245
 2008-03-11 21:29:43 +00:00
Chris Lattner
fd2c24af72 Implement basic support for the 'f' register class constraint. This basically 
works, but probably won't if you mix it with 't' or 'u' yet.

llvm-svn: 48243
 2008-03-11 19:50:13 +00:00
Evan Cheng
af1c76846d When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. 
llvm-svn: 48218
 2008-03-11 07:19:34 +00:00
Chris Lattner
f0684bfd16 Don't emit FP_REG_KILL into a block that just returns. Nothing 
can be live out of the block anyway, so it isn't needed.

llvm-svn: 48192
 2008-03-10 23:34:12 +00:00
Dan Gohman
47137eba06 Fix mul expansion to check the correct number of bits for 
zero extension when checking if an unsigned multiply is
safe.

llvm-svn: 48171
 2008-03-10 20:42:19 +00:00
Dale Johannesen
62a0b6a79b These tests don't work unless SSE2 is active. 
Judging from the checking comments this is intentional,
so add the flag (makes them pass on non-x86 host).

llvm-svn: 48157
 2008-03-10 17:33:57 +00:00
Dale Johannesen
c9ecee85c4 There is no "-mattr=+sse1" flag; fix test for non-x86 hosts. 
llvm-svn: 48156
 2008-03-10 17:13:37 +00:00
Evan Cheng
02b66c3a32 - Fix a subtle bug in RemoveCopyByCommutingDef. ALR is the live range where the source is defined; BLR is the live range which is defined by the copy. 
If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.                                                                                                 
 A = or A, B                                                                                                                                                            
 ...                                                                                                                                                                    
 B = A                                                                                                                                                                  
 ...                                                                                                                                                                    
 C = A<kill>                                                                                                                                                            
 ...                                                                                                                                                                    
   = B                                                                                                                                                                  
                                                                                                                                                                        
then do not add kills of A to the newly created B interval.
- Also fix some kill info update bug.

llvm-svn: 48141
 2008-03-10 08:11:32 +00:00
Evan Cheng
3c0ddc999f Avoid creating BUILD_VECTOR of all zero elements of "non-normalized" type (e.g. v8i16 on x86) after legalizer. Instruction selection does not expect to see them. In all likelihood this can only be an issue in a bugpoint reduced test case. 
llvm-svn: 48136
 2008-03-10 07:19:13 +00:00
Chris Lattner
b6bfedbcfd teach X86InstrInfo::copyRegToReg how to copy into ST(0) from 
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.

llvm-svn: 48107
 2008-03-09 09:15:31 +00:00
Chris Lattner
8d0203478f Add ScheduleDAG support for copytoreg where the src/dst register are 
in different register classes, e.g. copy of ST(0) to RFP*.  This gets
some really trivial inline asm working that plops things on the top of
stack (PR879)

llvm-svn: 48105
 2008-03-09 08:49:15 +00:00
Chris Lattner
b9a4c86fbf reduce this testcase more 
llvm-svn: 48092
 2008-03-09 06:57:21 +00:00
Chris Lattner
b628208161 Finish implementing a readme entry: when inserting an i64 variable 
into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48090
 2008-03-09 05:42:06 +00:00
Chris Lattner
17f68a3075 Implement a readme entry, compiling 
#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.

llvm-svn: 48063
 2008-03-09 01:05:04 +00:00
Chris Lattner
24031c9426 make this test harder 
llvm-svn: 48061
 2008-03-09 00:30:06 +00:00
Chris Lattner
7173d3bd70 Teach SD some vector identities, allowing us to compile vec_set-9 into: 
_test3:
	movd	%rdi, %xmm1
	#IMPLICIT_DEF %xmm0
	punpcklqdq	%xmm1, %xmm0
	ret

instead of:

_test3:
	#IMPLICIT_DEF %rax
	movd	%rax, %xmm0
	movd	%rdi, %xmm1
	punpcklqdq	%xmm1, %xmm0
	ret

This is still not ideal.  There is no reason to two xmm regs.

llvm-svn: 48058
 2008-03-08 23:43:36 +00:00
Evan Cheng
dba1dfe962 Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions. 
llvm-svn: 48042
 2008-03-08 00:58:38 +00:00
Chris Lattner
aa81dc7d21 mark frem as expand for all legal fp types on x86, regardless of whether 
we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006
 2008-03-07 06:36:32 +00:00