41790 Commits

Author SHA1 Message Date
Kuba Mracek
8c87177d0b Follow-up for r291289: Fix failing global_metadata_darwin.ll test
llvm-svn: 291292
2017-01-06 22:22:22 +00:00
Michal Gorny
22cda48e3b [llvm-config] Print --system-libs only when static linking
Modify the --system-libs option in llvm-config to print system libs only
when using static linking. The system libraries are irrelevant when
linking to a shared library since the library has appropriate library
dependencies embedded.

Modify the --system-libs test appropriately to force static linking, and
disable it if static libs are not available (i.e. BUILD_SHARED_LIBS is
enabled).

Differential Revision: https://reviews.llvm.org/D27805

llvm-svn: 291285
2017-01-06 21:33:54 +00:00
Michal Gorny
a44b476fd0 [cmake] Canonicalize CMake booleans to 0/1 for lit interop
Canonicalize all CMake booleans to 0/1 before passing them to lit, to
ensure that the Python side handles all of them consistently
and correctly. 0/1 is a safe choice of values that trigger the same
boolean interpretation in CMake, Python and C++.

Furthermore, using them without quotes improves the chance Python will
explicitly fail when an incorrect value (such as ON/OFF, TRUE/FALSE,
YES/NO) is accidentally passed, rather than silently misinterpreting
the value.

This replaces a lot of different logics spread around lit site files,
attempting to partially reproduce the boolean logic used in CMake
and usually silently failing when an uncommon value was used instead.
In fact, some of them were never working correctly since different
values were assigned in CMake and checked in Python.

The alternative solution could be to create a common parser for CMake
booleans in lit and use it consistently throughout the site files.
However, it does not seem like the best idea to create redundant
implementation of the same logic and have to follow upstream if it ever
is extended to handle more values.

Differential Revision: https://reviews.llvm.org/D28294

llvm-svn: 291284
2017-01-06 21:33:48 +00:00
Michal Gorny
564c4f1d2a [test] Remove unused 'test_examples' config var
Remove config.test_examples from lit.site.cfg and the relevant
ENABLE_EXAMPLES definition from CMake. It is not used anywhere.

Differential Revision: https://reviews.llvm.org/D28283

llvm-svn: 291283
2017-01-06 21:33:39 +00:00
David Majnemer
56f8a7c1a4 [InstSimplify] Optimize away urems in the presence of range metadata
We know that urem %V, C can be optimized away to %V if %V is ult C.

llvm-svn: 291282
2017-01-06 21:23:51 +00:00
Mehdi Amini
238fe14a1e Fix LoopLoadElimination to keep original alignment on the inital hoisted store
This is fixing a bug where Loop Vectorization is widening a load but
with a lower alignment. Hoisting the load without propagating the alignment
will allow inst-combine to later deduce a higher alignment that what the pointer
actually is.

Differential Revision: https://reviews.llvm.org/D28408

llvm-svn: 291281
2017-01-06 21:06:51 +00:00
Jan Vesely
523782f6c1 AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodes
This will make transition to SCRATCH_MEMORY easier

Differential Revision: https://reviews.llvm.org/D24746

llvm-svn: 291279
2017-01-06 21:00:46 +00:00
Simon Pilgrim
cf7fd92207 [X86][SSE] Standardized triples in vector shift tests
Made no sense for them to be different and caused useless diffs in assembly remarks.

llvm-svn: 291274
2017-01-06 19:56:57 +00:00
Simon Pilgrim
b938c434f9 [CostModel][X86] Add AVX512 and 512-bit vector shift cost tests.
llvm-svn: 291269
2017-01-06 19:41:26 +00:00
Matthias Braun
fcf8735ea4 AArch64CollectLOH: Rewrite as block-local analysis.
Re-apply r288561: This time with a fix where the ADDs that are part of a
3 instruction LOH would not invalidate the "LastAdrp" state. This fixes
http://llvm.org/PR31361

Previously this pass was using up to 5% compile time in some cases which
is a bit much for what it is doing. The pass featured a full blown
data-flow analysis which in the default configuration was restricted to a
single block.

This rewrites the pass under the assumption that we only ever work on a
single block. This is done in a single pass maintaining a state machine
per general purpose register to catch LOH patterns.

Differential Revision: https://reviews.llvm.org/D27329

This reverts commit 9e6cedb0a4f14364d6511597a9160305e7d34493.

llvm-svn: 291266
2017-01-06 19:22:01 +00:00
Sanjay Patel
bbb8bbf58b [InstCombine] add a vector version of a test added in r291262; NFC
llvm-svn: 291265
2017-01-06 19:14:05 +00:00
Sanjay Patel
e3702efb5f [InstCombine] move and add tests for icmp + shl nsw; NFC
As discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2017-January/108749.html
...we should be able to better optimize this pattern.

llvm-svn: 291262
2017-01-06 18:57:54 +00:00
Wolfgang Pieb
04238483a0 [DWARF] Null out the debug locs of (loop invariant) instructions hoisted by LICM in
order to avoid jumpy line tables. Calls are left alone because they may be inlined.

Differential Revision: https://reviews.llvm.org/D28390

llvm-svn: 291258
2017-01-06 18:38:57 +00:00
Chad Rosier
2e3e81f00b [AArch64] Reduce vector insert/extract cost for Falkor.
Differential Revision: https://reviews.llvm.org/D28403

llvm-svn: 291254
2017-01-06 18:03:26 +00:00
Konstantin Zhuravlyov
260cc2dc04 [AMDGPU] Do not emit .AMDGPU.config section for amdhsa
Differential Revision: https://reviews.llvm.org/D27732

llvm-svn: 291245
2017-01-06 17:02:10 +00:00
Simon Pilgrim
65eb262a86 [X86][AVX] Regenerate shuffle 128-bit tests.
The EVEX -> VEX fix means that AVX/AVX512 code is more likely the same now.

llvm-svn: 291242
2017-01-06 15:56:52 +00:00
Simon Pilgrim
0e61f9fdb1 [X86][AVX] Regenerate tzcnt tests.
The EVEX -> VEX fix means that AVX/AVX512 code is more likely the same now.

llvm-svn: 291241
2017-01-06 15:54:23 +00:00
Filipe Cabecinhas
368bad5905 [ASan] Make ASan instrument variable-masked loads and stores
Summary: Previously we only supported constant-masked loads and stores.

Reviewers: kcc, RKSimon, pgousseau, gbedwell, vitalybuka

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28370

llvm-svn: 291238
2017-01-06 15:24:51 +00:00
Simon Pilgrim
f29ec731bd [CostModel][X86] Fix 512-bit SDIV/UDIV 'big' costs.
Set the costs on the lowest target that supports the type.

llvm-svn: 291229
2017-01-06 11:12:53 +00:00
Simon Pilgrim
6597231ee4 [CostModel][X86] Add SDIV/UDIV cost tests for a wider range of targets
Added a test demonstrating bug in AVX512 division costs

llvm-svn: 291228
2017-01-06 11:02:40 +00:00
Daniel Jasper
bac44b8b6d Move test input to directory called Inputs.
It is a common convention that our internal test runner depends upon.

llvm-svn: 291227
2017-01-06 10:22:15 +00:00
Craig Topper
57aa6f2cf0 [AVX-512] Add EXTRACT_SUBVECTOR support to combineBitcastForMaskedOp.
llvm-svn: 291214
2017-01-06 05:18:48 +00:00
Craig Topper
505c94721c [AVX-512] Add more masked vector extract test cases with and without a bitcast between the select.
The ones with the bitcast need additional work to fold the mask operation properly. This will be fixed in a future commit.

llvm-svn: 291213
2017-01-06 05:18:44 +00:00
Peter Collingbourne
56f985d4fc LowerTypeTests: Split the pass in two: a resolution phase and a lowering phase.
This change separates how type identifiers are resolved from how intrinsic
calls are lowered. All information required to lower an intrinsic call
is stored in a new TypeIdLowering data structure. The idea is that this
data structure can either be initialized using the module itself during
regular LTO, or using the module summary in ThinLTO backends.

Differential Revision: https://reviews.llvm.org/D28341

llvm-svn: 291205
2017-01-06 02:22:47 +00:00
David Majnemer
f0ed7ae0f8 [SelectionDAG] Correctly transform range metadata to AssertZExt
We used the logBase2 of the high instead of the ceilLogBase2 resulting
in the wrong result for certain values.  For example, it resulted in an
i1 AssertZExt when the exclusive portion of the range was 3.

llvm-svn: 291196
2017-01-06 00:11:46 +00:00
Geoff Berry
976053d8f0 [AArch64] Fold some filled/spilled subreg COPYs
Summary:
Extend AArch64 foldMemoryOperandImpl() to handle folding spills of
subreg COPYs with read-undef defs like:

  %vreg0:sub_32<def,read-undef> = COPY %WZR; GPR64:%vreg0

by widening the spilled physical source reg and generating:

  STRXui %XZR <fi#0>

as well as folding fills of similar COPYs like:

  %vreg0:sub_32<def,read-undef> = COPY %vreg1; GPR64:%vreg0, GPR32:%vreg1

by generating:

  %vreg0:sub_32<def,read-undef> = LDRWui <fi#0>

Reviewers: MatzeB, qcolombet

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D27425

llvm-svn: 291180
2017-01-05 21:51:42 +00:00
Teresa Johnson
a5aad4bd67 ThinLTO: add early "dead-stripping" on the Index
Summary:
Using the linker-supplied list of "preserved" symbols, we can compute
the list of "dead" symbols, i.e. the one that are not reachable from
a "preserved" symbol transitively on the reference graph.
Right now we are using this information to mark these functions as
non-eligible for import.

The impact is two folds:
- Reduction of compile time: we don't import these functions anywhere
  or import the function these symbols are calling.
- The limited number of import/export leads to better internalization.

Patch originally by Mehdi Amini.

Reviewers: mehdi_amini, pcc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23488

llvm-svn: 291177
2017-01-05 21:34:18 +00:00
Joerg Sonnenberger
d01a38a2e3 PR 31534: When emitting both DWARF unwind tables and debug information,
do not use .cfi_sections. This requires checking if any non-declaration
function in the module needs an unwind table.

llvm-svn: 291172
2017-01-05 20:55:28 +00:00
Michael Kuperstein
5863ebbfd3 [LICM] Allow promotion of some stores that are not guaranteed to execute.
Promotion is always legal when a store within the loop is guaranteed to execute.

However, this is not a necessary condition - for promotion to be memory model
semantics-preserving, it is enough to have a store that dominates every exit
block. This is because if the store dominates every exit block, the fact the
exit block was executed implies the original store was executed as well.

Differential Revision: https://reviews.llvm.org/D28147

llvm-svn: 291171
2017-01-05 20:42:06 +00:00
Matthias Braun
61599008e2 CodeGen: Assert that liveness is up to date when reading block live-ins.
Add an assert that checks whether liveins are up to date before they are
used.

- Do not print liveins into .mir files anymore in situations where they
  are out of date anyway.
- The assert in the RegisterScavenger is superseded by the new one in
  livein_begin().
- Skip parts of the liveness updating logic in IfConversion.cpp when
  liveness isn't tracked anymore (just enough to avoid hitting the new
  assert()).

Differential Revision: https://reviews.llvm.org/D27562

llvm-svn: 291169
2017-01-05 20:01:19 +00:00
Sanjay Patel
a376165489 [x86] add test to show bug in select lowering; NFC
llvm-svn: 291151
2017-01-05 18:35:44 +00:00
Simon Pilgrim
87a1dcdf6d [CostModel][X86] Include the cost of 256-bit upper subvector extract/insertion in AVX1 v4i64 MUL
Matches other MUL/ADD/SUB 256-bit case on AVX1

llvm-svn: 291149
2017-01-05 18:20:25 +00:00
Chad Rosier
54356c6a0e [AArch64][CostModel] Add coverage for bswap intrinsics.
llvm-svn: 291140
2017-01-05 16:55:32 +00:00
Zvi Rackover
ba19393dad [X86] Add test cases that cover pr31551. NFC.
llvm-svn: 291127
2017-01-05 16:48:28 +00:00
Simon Pilgrim
e00b6e9f42 [CostModel][X86] Add support for broadcast shuffle costs
Currently only for broadcasts with input and output of the same width.

Differential Revision: https://reviews.llvm.org/D27811

llvm-svn: 291122
2017-01-05 15:56:08 +00:00
Zvi Rackover
7f372e97f6 [X86] Optimize vector shifts with variable but uniform shift amounts
Summary:
For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register.
The lower 64-bits of the register are evaluated to determine the shift amount.
This patch improves the construction of the vector containing the shift amount.

Reviewers: craig.topper, delena, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28353

llvm-svn: 291120
2017-01-05 15:11:43 +00:00
Chad Rosier
2caaab6e8f [AArch64] Remove mcpu option as this test is not target specific. NFC.
llvm-svn: 291117
2017-01-05 15:05:03 +00:00
Tony Jiang
87eac04da6 [PowerPC] Implement missing ISA 2.06 instructions.
Instructions: fctidu[.], fctiwu[.], ftdiv, ftsqrt are not implemented. Implement
them and add corresponding test cases in this patch.

llvm-svn: 291116
2017-01-05 15:00:45 +00:00
Chad Rosier
4891053009 [AArch64] Remove unused arguments from tests. NFC.
llvm-svn: 291112
2017-01-05 14:48:53 +00:00
Teresa Johnson
1bdb8a9032 [ThinLTO] Subsume all importing checks into a single flag
Summary:
This adds a new summary flag NotEligibleToImport that subsumes
several existing flags (NoRename, HasInlineAsmMaybeReferencingInternal
and IsNotViableToInline). It also subsumes the checking of references
on the summary that was being done during the thin link by
eligibleForImport() for each candidate. It is much more efficient to
do that checking once during the per-module summary build and record
it in the summary.

Reviewers: mehdi_amini

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28169

llvm-svn: 291108
2017-01-05 14:32:16 +00:00
Mohammed Agabaria
caef091029 Currently isLikelyComplexAddressComputation tries to figure out if the given stride seems to be 'complex' and need some extra cost for address computation handling.
This code seems to be target dependent which may not be the same for all targets.
Passed the decision whether the given stride is complex or not to the target by sending stride information via SCEV to getAddressComputationCost instead of 'IsComplex'.

Specifically at X86 targets we dont see any significant address computation cost in case of the strided access in general.

Differential Revision: https://reviews.llvm.org/D27518

llvm-svn: 291106
2017-01-05 14:03:41 +00:00
Kristof Beyls
a124ec224e [GlobalISel] Add support for address-taken basic blocks
To make this work, pointers from the MachineBasicBlock to the LLVM-IR-level
basic blocks need to be initialized, as the AsmPrinter uses this link to be
able to print out labels for the basic blocks that are address-taken.

Most of the changes in this commit are about adapting existing tests to include
the basic block name that is now printed out in the MIR format, now that the
name becomes available as the link to the LLVM-IR basic block is initialized.
The relevant test change for the functionality added in this patch are the
added "(address-taken)" strings in
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll.

Differential Revision: https://reviews.llvm.org/D28123

llvm-svn: 291105
2017-01-05 13:27:52 +00:00
Kristof Beyls
1ab23a98c0 [GlobalISel] Add support for switch statements
This commit does this using a trivial chain of conditional branches.  In the
future, we probably want to reuse the optimized switch lowering used in
SelectionDAG.

Differential Revision: https://reviews.llvm.org/D28176

llvm-svn: 291099
2017-01-05 11:28:51 +00:00
Kristof Beyls
092ee33045 [GlobalISel] Fix AArch64 ICMP instruction selection
Differential Revision: https://reviews.llvm.org/D28175

llvm-svn: 291097
2017-01-05 10:16:08 +00:00
Elena Demikhovsky
d697873892 AVX-512: Optimized pattern for truncate with unsigned saturation.
DAG patterns optimization: truncate + unsigned saturation supported by VPMOVUS* instructions in AVX-512.
Differential revision: https://reviews.llvm.org/D28216

llvm-svn: 291092
2017-01-05 08:21:09 +00:00
Saleem Abdulrasool
442a13cb03 test: remove unnecessary triple argument
This test is entirely target agnostic.  Avoid the triple to repair the
build bots.

llvm-svn: 291088
2017-01-05 06:30:12 +00:00
Saleem Abdulrasool
939d0790a2 MC: support passing search paths to the IAS
This is needed to support inclusion in inline assembly via the
`.include` directive.

llvm-svn: 291085
2017-01-05 05:56:39 +00:00
Peter Collingbourne
714dbaced0 IR: Module summary representation for type identifiers; summary test scaffolding for lowertypetests.
Set up basic YAML I/O support for module summaries, plumb the summary into
the pass and add a few command line flags to test YAML I/O support. Bitcode
support to come separately, as will the code in LowerTypeTests that actually
uses the summary. Also add a couple of tests that pass by virtue of the pass
doing nothing with the summary (which happens to be the correct thing to do
for those tests).

Differential Revision: https://reviews.llvm.org/D28041

llvm-svn: 291069
2017-01-05 03:39:00 +00:00
Craig Topper
4ca56e7a5d [AVX-512] Update vextract64x4 intrinsic upgrade test cases to use a legal immediate so they test the instruction selection correctly.
llvm-svn: 291061
2017-01-05 01:34:55 +00:00
Mehdi Amini
fa8809adfa Mark test that is testing statistics output as requiring Assertions
We only enable statistic in an assert build by default.

llvm-svn: 291044
2017-01-05 01:08:01 +00:00