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76 Commits

Author SHA1 Message Date
Bob Wilson
9501c478f7 Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
 2010-03-19 22:51:32 +00:00
Anton Korobeynikov
eeae840ed7 Get rid of target-specific fp <-> int nodes when still I'm here. 
llvm-svn: 98889
 2010-03-18 22:35:45 +00:00
Anton Korobeynikov
23c07f492e Get rid of target-specific nodes for fp16 <-> fp32 conversion. 
llvm-svn: 98888
 2010-03-18 22:35:37 +00:00
Johnny Chen
54bb1efbe0 Disambiguate the *_UPD and * variants by specifying the writeback flag as 1. 
This is for the disassembly work.

There are cases where this is not possible, for example, A8.6.53 LDM Encoding T1.
In such case, we'll use an adhoc approach to deduce the Opcode programmatically.

llvm-svn: 98679
 2010-03-16 21:25:05 +00:00
Bob Wilson
aee6e76a7d Remove redundant writeback flag in ARM addressing mode 5. 
llvm-svn: 98648
 2010-03-16 18:38:09 +00:00
Anton Korobeynikov
48357cdc62 Add codegen support for FP16 on ARM 
llvm-svn: 98502
 2010-03-14 18:42:31 +00:00
Bob Wilson
163aa28fa1 Attempt to appease the arm-linux buildbot by fixing the JIT encodings for new 
base register updating load/store-multiple instructions.

llvm-svn: 98427
 2010-03-13 07:34:35 +00:00
Bob Wilson
0e8a3d7a13 Change ARM ld/st multiple instructions to have variant instructions for 
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.

llvm-svn: 98409
 2010-03-13 01:08:20 +00:00
Chris Lattner
49ef2cd57b fix a bunch of partially ambiguous patterns on ARM. As an 
example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.

llvm-svn: 97955
 2010-03-08 18:51:21 +00:00
Dan Gohman
99c6bcbc13 The mayHaveSideEffects flag is no longer used. 
llvm-svn: 97348
 2010-02-27 23:47:46 +00:00
Johnny Chen
7c088ab119 Added VCVT (between floating-point and fixed-point, VFP) for disassembly. 
A8.6.297

llvm-svn: 95885
 2010-02-11 18:17:16 +00:00
Johnny Chen
15da54da55 Added VMRS/VMSR for disassembly only. 
A8.6.335 & A8.6.336

llvm-svn: 95703
 2010-02-09 22:35:38 +00:00
Johnny Chen
de3621cfa8 Added vcvtb/vcvtt (between half-precision and single-precision, VFP). 
For disassembly only.

A8.6.300

llvm-svn: 95669
 2010-02-09 17:21:56 +00:00
Johnny Chen
396391964d Add VCVTR (between floating-point and integer, VFP) for disassembly purpose. 
The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584
 2010-02-08 22:02:41 +00:00
Johnny Chen
7092ebb040 Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose. 
llvm-svn: 95560
 2010-02-08 19:41:48 +00:00
Johnny Chen
92ec9f2887 Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose. 
A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548
 2010-02-08 17:26:09 +00:00
Johnny Chen
0b398e3919 VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00. 
llvm-svn: 95397
 2010-02-05 18:04:58 +00:00
Johnny Chen
377da9a33c Modified encoding bits specification for VFP instructions. In particular, the D 
bit (Inst{22}) and the M bit (Inst{5}) should be left unspecified.  For binary
format instructions, Inst{6} and Inst{4} need to specified for proper decodings.

llvm-svn: 94855
 2010-01-29 23:21:10 +00:00
Evan Cheng
179a11776c Data type suffix must come after predicate. 
llvm-svn: 89723
 2009-11-24 01:05:23 +00:00
Jim Grosbach
76b545e988 move fconst[sd] to UAL. <rdar://7414913> 
llvm-svn: 89700
 2009-11-23 21:08:25 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Jim Grosbach
85faa3cff1 use lower case for readability 
llvm-svn: 87054
 2009-11-13 01:17:22 +00:00
Evan Cheng
2c0fc2e713 Add a comment. 
llvm-svn: 86706
 2009-11-10 19:44:56 +00:00
Jim Grosbach
5b33ce12e3 Work around assembler not recognizing #0.0 form immediate for vmcp 
llvm-svn: 86548
 2009-11-09 15:27:51 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Evan Cheng
519b231883 fconsts and fconstd are obviously re-materializable. 
llvm-svn: 85410
 2009-10-28 18:19:56 +00:00
Evan Cheng
1babe43881 Use fconsts and fconstd to materialize small fp constants. 
llvm-svn: 85362
 2009-10-28 01:44:26 +00:00
Evan Cheng
032eef9720 Now VFP instructions. 
llvm-svn: 85186
 2009-10-27 00:20:49 +00:00
Evan Cheng
241092d89f Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.

llvm-svn: 83197
 2009-10-01 08:22:27 +00:00
Evan Cheng
4dd7d7156e Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
llvm-svn: 83191
 2009-10-01 01:33:39 +00:00
David Goodwin
89f5854ddd Finish scheduling itineraries for NEON. 
llvm-svn: 82788
 2009-09-25 18:38:29 +00:00
David Goodwin
0db84be1dc Add Cortex-A8 VFP model. 
llvm-svn: 82483
 2009-09-21 20:52:17 +00:00
David Goodwin
36a5b02e4f Use NEON for single-precision int<->FP conversions. 
llvm-svn: 78604
 2009-08-10 22:17:39 +00:00
David Goodwin
3aafcc1dd2 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
David Goodwin
648590849c Add NEON single-precision FP support for fabs and fneg. 
llvm-svn: 78101
 2009-08-04 20:39:05 +00:00
David Goodwin
5efde448fa Match common pattern for FNMAC. Add NEON SP support. 
llvm-svn: 78085
 2009-08-04 18:44:29 +00:00
David Goodwin
99adffe5f2 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Evan Cheng
2f6b299d6f Model fpscr to prevent fcmped / fcmpezs etc from being deleted. 
llvm-svn: 76390
 2009-07-20 02:12:31 +00:00
David Goodwin
1a6f4f6f8d Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2. 
llvm-svn: 75254
 2009-07-10 17:03:29 +00:00
Evan Cheng
2f784781aa Mark some pattern-less instructions as neverHasSideEffects. 
llvm-svn: 73252
 2009-06-12 20:46:18 +00:00
Evan Cheng
dfa19a4009 Fix a 80 col. violation. 
llvm-svn: 60901
 2008-12-11 22:02:02 +00:00
Dan Gohman
5dad0993a9 Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
llvm-svn: 60487
 2008-12-03 18:15:48 +00:00
Evan Cheng
7ac8120105 Fix fuitos encoding. 
llvm-svn: 59344
 2008-11-15 00:40:57 +00:00
Evan Cheng
997eb67c20 fsub{d|s} encoding bugs. 
llvm-svn: 59234
 2008-11-13 07:59:48 +00:00
Evan Cheng
7fef8cfe75 Consolidate formats; fix FCMPED etc. encodings. 
llvm-svn: 59107
 2008-11-12 07:18:38 +00:00
Evan Cheng
0966883093 Fix VFP conversion instruction encodings. 
llvm-svn: 59104
 2008-11-12 06:41:41 +00:00
Evan Cheng
39d8bf295d Fix encoding of single-precision VFP registers. 
llvm-svn: 59102
 2008-11-12 02:19:38 +00:00
Evan Cheng
8b7fefc126 Fix FMDRR encoding. 
llvm-svn: 59088
 2008-11-11 22:46:12 +00:00
Evan Cheng
35f1477c5a Encode VFP load / store instructions. 
llvm-svn: 59084
 2008-11-11 21:48:44 +00:00
Evan Cheng
91e4ef91c5 Encode VFP conversion instructions. 
llvm-svn: 59074
 2008-11-11 19:40:26 +00:00