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95987c2586
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8367 Commits

Author SHA1 Message Date
Evan Cheng
95987c2586 Doh. Alignment is in bytes, not in bits. 
llvm-svn: 51092
 2008-05-14 02:49:43 +00:00
Dan Gohman
f9d5689496 Change target-specific classes to use more precise static types. 
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091
 2008-05-14 01:58:56 +00:00
Chris Lattner
a11adf725d add a note 
llvm-svn: 51062
 2008-05-13 19:56:20 +00:00
Evan Cheng
cb56638548 - Fix the pasto in the fix for a previous pasto. 
- Incorporate Chris' comment suggestion.

llvm-svn: 51061
 2008-05-13 18:59:59 +00:00
Chris Lattner
c9eb6a7d64 add a note 
llvm-svn: 51060
 2008-05-13 18:48:54 +00:00
Nate Begeman
c290daf581 Fix one more encoding bug. 
llvm-svn: 51057
 2008-05-13 17:52:09 +00:00
Evan Cheng
cf6928983b - Don't treat anyext 16-bit load as a 32-bit load if it's volatile. 
- Correct a pasto.

llvm-svn: 51054
 2008-05-13 16:45:56 +00:00
Sanjiv Gupta
fa065a1455 Adding files for Microchip's PIC16 target. 
A brief description about PIC16:
===============================
PIC16 is an 8-bit microcontroller with only one 8-bit register which is the 
accumulator. All arithmetic/load/store operations are 8-bit only.
The architecture has two address spaces: program and data. The program memory 
is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory. 

It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register). 

Two classes of registers exist: (8-bit class which is only one
accumulator) (16-bit class, which contains one or more 16 bit
pointer(s))

llvm-svn: 51027
 2008-05-13 09:02:57 +00:00
Evan Cheng
9e15622879 Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset. 
pshufd $1, (%rdi), %xmm0
        movd %xmm0, %eax
=>
        movl 4(%rdi), %eax

llvm-svn: 51026
 2008-05-13 08:35:03 +00:00
Nate Begeman
b9a3d141aa Fix and encoding error in the psrad xmm, imm8 instruction. 
llvm-svn: 51020
 2008-05-13 01:47:52 +00:00
Evan Cheng
e4ee4c2870 On x86, it's safe to treat i32 load anyext as a normal i32 load. Ditto for i8 anyext load to i16. 
llvm-svn: 51019
 2008-05-13 00:54:02 +00:00
Dan Gohman
bab18cae46 Clean up the use of static and anonymous namespaces. This turned up 
several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017
 2008-05-13 00:00:25 +00:00
Nate Begeman
5d939498c3 Teach Legalize how to scalarize VSETCC 
Teach X86 a few more vsetcc patterns.  Custom lowering for unsupported ones is next.

llvm-svn: 51009
 2008-05-12 23:09:43 +00:00
Evan Cheng
fcbdc8bd6e Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other. 
llvm-svn: 51008
 2008-05-12 23:04:07 +00:00
Bill Wendling
646f3458c4 Constify the machine instruction passed into the 
"is{Trivially,Really}ReMaterializable" methods.

llvm-svn: 51001
 2008-05-12 20:54:26 +00:00
Nate Begeman
2ae55cecc6 Initial X86 codegen support for VSETCC. 
llvm-svn: 51000
 2008-05-12 20:34:32 +00:00
Dan Gohman
efa0925915 Fix a copy+paste bug; pseudo-instructions shouldn't have 
encoding information.

llvm-svn: 50997
 2008-05-12 20:22:45 +00:00
Evan Cheng
c7e9acfed7 Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. 
llvm-svn: 50991
 2008-05-12 19:56:52 +00:00
Nate Begeman
11c0772a30 Add support for vicmp/vfcmp codegen, more legalize support coming. 
This is necessary to unbreak the build.

llvm-svn: 50988
 2008-05-12 19:40:03 +00:00
Dan Gohman
8212eaa43a Fix a compile error on compilers that still want a return value 
in a non-void function that calls abort.

llvm-svn: 50969
 2008-05-12 16:17:19 +00:00
Anton Korobeynikov
ad83aeb489 Add note 
llvm-svn: 50959
 2008-05-11 14:33:15 +00:00
Evan Cheng
c19c639ad7 When transforming a vector_shuffle to a load, the base address must not be an undef. 
llvm-svn: 50940
 2008-05-10 06:46:49 +00:00
Dan Gohman
4b23d9e60a For now, abort when an ISD::VAARG is encountered on x86-64, rather 
than silently generate invalid code.

llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.

llvm-svn: 50930
 2008-05-10 01:26:14 +00:00
Evan Cheng
6a3fa28b38 Some clean up. 
llvm-svn: 50929
 2008-05-10 00:59:18 +00:00
Evan Cheng
79230955a8 If movl top bits are undef, let it be selected to movlps, etc. 
llvm-svn: 50928
 2008-05-10 00:58:41 +00:00
Evan Cheng
2adea48f7e Add a pattern to do move the low element of a v4f32 and zero extend the rest. 
llvm-svn: 50922
 2008-05-09 23:37:55 +00:00
Evan Cheng
3493e43afd Handle a few more cases of folding load i64 into xmm and zero top bits. 
Note, some of the code will be moved into target independent part of DAG combiner in a subsequent patch.

llvm-svn: 50918
 2008-05-09 21:53:03 +00:00
Evan Cheng
f824b47188 Use movq to move low half of XMM register and zero-extend the rest. 
llvm-svn: 50874
 2008-05-08 22:35:02 +00:00
Evan Cheng
f97e716511 Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. 
llvm-svn: 50838
 2008-05-08 00:57:18 +00:00
Duncan Sands
6f4e916c6a Output correct exception handling and frame info 
on x86-64 linux.  This causes no regressions on
32 bit linux and 32 bit ppc.  More tests pass
on 64 bit ppc with no regressions.  I didn't
turn on eh on 64 bit linux because the intrinsics
needed to compile the eh runtime aren't done
yet.  But if you turn it on and link with the
mainline runtime then eh seems to work fine
on x86-64 linux with this patch.  Thanks to
Dale for testing.  The main point of the patch
is that if you output that some object is
encoded using 4 bytes you had better not output
8 bytes for it: the patch makes everything
consistent.

llvm-svn: 50825
 2008-05-07 19:11:09 +00:00
Chris Lattner
d46c148cf8 Match things like 'armv5tejl-unknown-linux-gnu' for PR2290 
llvm-svn: 50698
 2008-05-06 02:29:28 +00:00
Dan Gohman
d4a670284c Make several variable declarations static. 
llvm-svn: 50696
 2008-05-06 01:53:16 +00:00
Chris Lattner
9f4f2444ea add a micro optzn. 
llvm-svn: 50681
 2008-05-05 23:19:45 +00:00
Mon P Wang
34b3f18a70 Improved generated code for atomic operators 
llvm-svn: 50677
 2008-05-05 22:56:23 +00:00
Evan Cheng
44d49e72a1 Code clean up. No functionality change. 
llvm-svn: 50675
 2008-05-05 22:12:23 +00:00
Mon P Wang
84a269e023 Added addition atomic instrinsics and, or, xor, min, and max. 
llvm-svn: 50663
 2008-05-05 19:05:59 +00:00
Dan Gohman
4a674dc536 Fix IsLinux being uninitialized on non-Linux targets. 
llvm-svn: 50660
 2008-05-05 18:43:07 +00:00
Anton Korobeynikov
12c48230f9 Fix 80col violation 
llvm-svn: 50654
 2008-05-05 17:08:59 +00:00
Dan Gohman
8ee7bf053e Use a dedicated IsLinux flag instead of an ELFLinux TargetType. 
llvm-svn: 50649
 2008-05-05 16:11:31 +00:00
Dan Gohman
c860d9c77c Add AsmPrinter support for emitting a directive to declare that 
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 

llvm-svn: 50634
 2008-05-05 00:28:39 +00:00
Anton Korobeynikov
04c974b1b2 Add General Dynamic TLS model for X86-64. Some parts looks really ugly (look for tlsaddr pattern), 
but should work. Work is in progress, more models will follow

llvm-svn: 50630
 2008-05-04 21:36:32 +00:00
Evan Cheng
a7747df955 Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register. 
llvm-svn: 50619
 2008-05-04 09:15:50 +00:00
Evan Cheng
c1c2adbfc6 Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code. 
llvm-svn: 50601
 2008-05-03 00:52:09 +00:00
Evan Cheng
90b9027f68 Undo r50574. We are already ensuring the folded load address is 16-byte aligned. 
llvm-svn: 50578
 2008-05-02 17:01:01 +00:00
Evan Cheng
583a346ec6 80 column violation. 
llvm-svn: 50575
 2008-05-02 07:53:32 +00:00
Evan Cheng
862e3a147c Not safe folding a load + FsXORPSrr into FsXORPSrm. It's loading a FR64 value but the load folding variant expects a 16-byte aligned address. 
llvm-svn: 50574
 2008-05-02 07:50:58 +00:00
Arnold Schwaighofer
f58a35e2ec Tail call optimization improvements: 
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.

Initial PowerPC tail call implementation:

Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).  
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if 
  caller and callee are fastcc
  call is a tail call (in tail call position, call followed by ret)
  no variable argument lists or byval arguments
  option -tailcallopt is enabled
Supported:
 * non pic tail calls on linux/darwin
 * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
 * inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.

A test checking the argument lowering behaviour on x86-64 was added.

llvm-svn: 50477
 2008-04-30 09:16:33 +00:00
Scott Michel
9dec950785 Bug fixes and updates for CellSPU, syncing up with trunk. Most notable 
fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().

llvm-svn: 50462
 2008-04-30 00:30:08 +00:00
Anton Korobeynikov
2dca0c7323 Don't do stupid things: doInitialization(Module&) is not applicable to ModulePass :) 
llvm-svn: 50433
 2008-04-29 18:16:22 +00:00
Dan Gohman
0285c1e9bb Fix the SVOffset values for loads and stores produced by 
memcpy/memset expansion. It was a bug for the SVOffset value
to be used in the actual address calculations.

llvm-svn: 50359
 2008-04-28 17:15:20 +00:00