Commit Graph

17933 Commits

Author SHA1 Message Date
Eli Friedman
66d3e9e11f Chris fixed this README a while back by changing how clang generates code for structs like the given struct.
llvm-svn: 132815
2011-06-09 23:02:19 +00:00
Cameron Zwarich
af47f4a117 A CCState was being created without setting whether it is in the Call or Prologue state,
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

llvm-svn: 132811
2011-06-09 22:30:07 +00:00
Roman Divacky
9b1aea9b45 Fix emission of PPC64 assembler on non-darwin platforms by splitting
VK_PPC_{HA,LO}16 into darwin and gas variants.

Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.

llvm-svn: 132802
2011-06-09 20:25:38 +00:00
Eli Friedman
f2dbd3e767 Revert 132789; it breaks tests. My mistake.
llvm-svn: 132795
2011-06-09 19:33:30 +00:00
Eli Friedman
d04e75fca2 Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.
llvm-svn: 132789
2011-06-09 18:55:00 +00:00
Jakob Stoklund Olesen
164dc685e5 Remove custom allocation order boilerplate that is no longer needed.
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781
2011-06-09 16:56:59 +00:00
Eric Christopher
24dafa3dbc Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
Duncan Sands
a0c88a5dd5 Enable printf() to iprintf() optimization for the TCE target.
Patch by Pekka Jaaskelainen. 

llvm-svn: 132774
2011-06-09 11:11:45 +00:00
Akira Hatanaka
33ec063f3b Initial support for inline asm memory operand constraints.
llvm-svn: 132768
2011-06-09 03:31:05 +00:00
Eric Christopher
1ae9ec6124 Add a parameter to CCState so that it can access the MachineFunction.
No functional change.

Part of PR6965

llvm-svn: 132763
2011-06-08 23:55:35 +00:00
Akira Hatanaka
38115eb019 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
dynamically allocated stack area was not set.

llvm-svn: 132758
2011-06-08 21:28:09 +00:00
Akira Hatanaka
ea8ce56dbb Reorganize code in MipsTargetLowering::LowerCall to improve readability.
llvm-svn: 132756
2011-06-08 17:39:33 +00:00
Akira Hatanaka
101d50423a Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
llvm-svn: 132726
2011-06-07 19:28:39 +00:00
Akira Hatanaka
e56d1fa083 Put back removed line.
llvm-svn: 132725
2011-06-07 19:03:14 +00:00
Akira Hatanaka
3b7982650c Coding style fixes.
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.

llvm-svn: 132724
2011-06-07 18:58:42 +00:00
Akira Hatanaka
f56f544d80 Use tabs to separate opcode and operand strings.
llvm-svn: 132718
2011-06-07 18:16:51 +00:00
Akira Hatanaka
fe54bb9de1 Add comments for wrapper node patterns in MipsInstrInfo.td.
llvm-svn: 132717
2011-06-07 18:00:14 +00:00
Akira Hatanaka
fbeb14925f Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 

llvm-svn: 132703
2011-06-07 02:17:21 +00:00
Andrew Trick
a46c28e96c Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.
rdar://problem/9556069

llvm-svn: 132699
2011-06-07 00:08:49 +00:00
Stuart Hastings
d044ba7a9f Followup to 132458, omit unnecessary stack copy when x87 input is a
load.  rdar://problem/6373334

llvm-svn: 132696
2011-06-06 23:15:58 +00:00
Stuart Hastings
ea8b49dff3 Reapply 132424 with fixes. This fixes PR10068.
rdar://problem/5993888

llvm-svn: 132606
2011-06-03 23:53:54 +00:00
Jakob Stoklund Olesen
0ac5f2eaf8 Blackfin always uses a reserved call frame.
Materializing the stack pointer update before a call requires a scratch
register that may not be available.

llvm-svn: 132601
2011-06-03 22:45:18 +00:00
Eric Christopher
e831655dd9 Make the Uv constraint a memory operand. This doesn't solve the
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561
2011-06-03 17:24:37 +00:00
Roman Divacky
3624922127 Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.

llvm-svn: 132552
2011-06-03 15:47:49 +00:00
Eli Friedman
eae10d6163 Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
rdar://9431157

llvm-svn: 132522
2011-06-03 01:13:19 +00:00
Eric Christopher
d68494ffdd Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939

llvm-svn: 132510
2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen
409986a648 Flag unallocatable register classes instead of giving them empty
allocation orders.

llvm-svn: 132509
2011-06-02 23:07:24 +00:00
Jakob Stoklund Olesen
4f76a2bdc8 Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508
2011-06-02 23:07:20 +00:00
Tanya Lattner
aa1f6df650 Fix encoding for VEXTdf.
llvm-svn: 132486
2011-06-02 21:25:24 +00:00
Rafael Espindola
1299f014d4 Revert 132424 to fix PR10068.
llvm-svn: 132479
2011-06-02 19:57:47 +00:00
Stuart Hastings
8447f18f85 Omit unnecessary stack copy when x87 input is a load.
rdar://problem/6373334

llvm-svn: 132458
2011-06-02 15:57:11 +00:00
Jakob Stoklund Olesen
25716baae0 Use TRI::has{Sub,Super}ClassEq() where possible.
No functional change.

llvm-svn: 132455
2011-06-02 05:43:46 +00:00
Rafael Espindola
ee123951a2 Don't hardcode the %reg format in the streamer.
llvm-svn: 132451
2011-06-02 02:34:55 +00:00
Akira Hatanaka
1f91013bcb Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.
llvm-svn: 132448
2011-06-02 01:03:14 +00:00
Akira Hatanaka
69ae562f33 Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
llvm-svn: 132444
2011-06-02 00:24:44 +00:00
Stuart Hastings
9a085fb9d8 Recommit 132404 with fixes. rdar://problem/5993888
llvm-svn: 132424
2011-06-01 21:33:14 +00:00
Stuart Hastings
4b33767382 Revert 132404 to appease a buildbot. rdar://problem/5993888
llvm-svn: 132419
2011-06-01 19:52:20 +00:00
Stuart Hastings
23f5ceda96 Add support for x86 CMPEQSS and friends. These instructions do a
floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404
2011-06-01 17:17:45 +00:00
Jakob Stoklund Olesen
283a7e46b5 Fix PR10059 and future variations by handling all register subclasses.
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398
2011-06-01 15:32:10 +00:00
Stuart Hastings
fdc9e4af68 FGETSIGN support for x86, using movmskps/pd. Will be enabled with a
patch to TargetLowering.cpp.  rdar://problem/5660695

llvm-svn: 132388
2011-06-01 04:39:42 +00:00
Bruno Cardoso Lopes
9231127d37 Fix uninitialized variables and silence warnings
llvm-svn: 132355
2011-05-31 20:25:26 +00:00
Richard Osborne
660fe84614 Fix 80 column violations.
llvm-svn: 132341
2011-05-31 16:30:33 +00:00
Richard Osborne
4293c93896 Add XCore intrinsic for crc8.
llvm-svn: 132340
2011-05-31 16:24:49 +00:00
Richard Osborne
34a4652dcd Add XCore intrinsic for crc32.
llvm-svn: 132336
2011-05-31 14:47:36 +00:00
Bruno Cardoso Lopes
0bdb365634 Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

llvm-svn: 132324
2011-05-31 03:33:27 +00:00
Bruno Cardoso Lopes
728ea362c3 This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323
2011-05-31 02:54:07 +00:00
Bruno Cardoso Lopes
f6fa29e7a1 This patch implements the thread local storage. Implemented are General
Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322
2011-05-31 02:53:58 +00:00
Rafael Espindola
33f7d7f9fa Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

llvm-svn: 132317
2011-05-30 20:20:15 +00:00
Rafael Espindola
13607c5e91 Split ppc dwarf regnums into ppc64 and ppc32 flavours.
llvm-svn: 132315
2011-05-30 18:24:44 +00:00
Rafael Espindola
5917c1f6ec Introduce the DwarfRegAlias class for declaring that two registers have the
same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

llvm-svn: 132314
2011-05-30 17:49:59 +00:00